Active solid-state devices (e.g. – transistors – solid-state diode – With means to control surface effects – Insulating coating
Reexamination Certificate
1998-06-10
2001-05-29
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
With means to control surface effects
Insulating coating
C257S213000, C257S214000, C257S215000, C257S752000, C257S753000, C257S754000, C257S755000, C257S756000, C438S587000, C438S702000, C438S911000
Reexamination Certificate
active
06239478
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a semiconductor structure for an MOS transistor with a substrate, a gate oxide and a polysilicon layer lying above it. Furthermore, the invention relates to a method for fabricating such a semiconductor structure.
Integrated MOS circuits, and in particular CMOS circuits, are fabricated with various methods in which the well dopants are generally introduced and implanted by temperature treatment. Then, isolation areas are produced by local oxidation of silicon (LOCOS) or shallow trench isolation (STI). After the isolation areas have been produced, a gate oxide is grown on the active areas by thermal oxidation and covered with a gate electrode which is preferably composed of polysilicon. The polysilicon is structured with a resist mask and reactive ion etching (RIE). The etching must thereby be sufficiently selective with respect to the gate oxide underneath, so that the substrate is not attacked during the etching. The production of the integrated circuit is then continued in a known manner.
Two significant problems, amongst others, arise during the fabrication of such integrated MOS transistors, and in particular of CMOS transistors. One problem relates to the quality of the gate oxide and the other to the topology during the structuring of the gate electrode. The quality of the gate oxide is essentially characterized by the defect density and the breakdown field strength. As the number of process steps involved in the production of the gate oxide increases, the quality of the gate oxide becomes worse, since each preceding process step increases the defect density and the surface becomes increasingly uneven. Therefore, it is desirable to produce the gate oxide as early as possible, i.e., during one of the first process steps, and to cover it with a gate electrode.
When the insulation of integrated CMOS circuits is produced by means of the local oxidation technique (LOCOS), for example, there is always a topology step at the junction between the active region and the insulation area. That topology step is of the order of magnitude of the thickness of the gate electrode, and is thus in the range of approximately 0.5 &mgr;m. As a result of different resist thicknesses and reflections at the field oxide edge, this has a disadvantageous effect on the dimensional accuracy during the structuring of the gate electrode. Furthermore, a spacer is formed at the field oxide step, so that the gate electrode is significantly thicker at this point than in the other areas. The greater thickness at this point must be allowed for by means of a longer etching time. However, on the other hand the etching must not continue through the extremely thin gate oxide and into the substrate. For a given level of the topology step at the field oxide edge this results in a very high etching selectivity and/or a correspondingly thick gate oxide.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a semiconductor structure for a MOS transistor, in particular a CMOS transistor, and a method for fabricating the semiconductor structure, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and which structure has a particularly good gate oxide quality and a largely regular topology in order to avoid the overetching problem with the gate electrode at the field oxide edge.
With the foregoing and other objects in view there is provided, in accordance with the invention, a semiconductor structure for a MOS transistor, comprising:
a substrate, a gate oxide on the substrate, and a polysilicon layer on the gate oxide;
the polysilicon layer having interruptions formed therein, and defining field plates and a polysilicon layer in an active area of the semiconductor structure;
insulating oxide disposed above the field plates and in the interruptions in the polysilicon layer;
and a further polysilicon deposition on the polysilicon layer in the active area, the deposition raising up the polysilicon layer in the active area to a level being substantially coplanar with the insulating oxide above the field plates.
In other words, the polysilicon layer has interruptions and forms field plates and a polysilicon layer in the active area. An insulating oxide is provided above the field plates and in the interruptions in the polysilicon layer. The polysilicon layer is raised in the active area, with the further polysilicon deposition, to such an extent that the polysilicon forms a plane with the insulating oxide above the field plates in the active area.
The foregoing semiconductor structure is preferably produced, in accordance with the invention, by a method which comprises the following step:
a) producing a gate oxide and a polysilicon layer on a substrate;
b) depositing a dielectric on the polysilicon layer;
c) structuring the dielectric and forming active areas;
d) fabricating spacers at edges produced during the structuring step;
e) partially oxidizing the polysilicon layer between the spacers;
f) removing the spacers, and removing the polysilicon of the polysilicon layer underneath the spacers isotropically;
g) conformally depositing an oxide;
h) spacer-etching of the oxide deposited in step g), and also removing, in the active area, oxide produced in step e); and
i) depositing silicon in the active area to a level of an adjoining oxide structure.
In other words, a gate oxide and a polysilicon layer are produced on a substrate, a dielectric is deposited on the polysilicon layer, the dielectric is structured in order to form active areas, a spacer is fabricated at edges produced during the structuring, the polysilicon layer is partially oxidized between these spacers, the spacers are removed, the polysilicon of the polysilicon layer under the spacers is removed anisotropically, an oxide is deposited in a conformal way, spacer etching which, in the active area, also removes the oxide produced previously, is carried out on the deposited oxide, and silicon is deposited in the active area to the level of the adjoining oxide structure.
Accordingly, a semiconductor structure for a MOS transistor and in particular a CMOS transistor with field plate isolation is created. In the process, a first oxide is used as gate oxide and the first polysilicon layer which is deposited thereon is simultaneously used as part of the gate electrode and as field plate layer outside the active areas. The gate oxide and the first polysilicon layer are produced at the start of the process sequence, as a result of which an optimum gate oxide quality is achieved. The gate areas are separated from the isolation areas in a self-aligned fashion by means of microtrench etching. These trenches are filled in by means of a spacer. A further polysilicon layer is selectively deposited on the exposed, first polysilicon areas, the thickness of which is selected to be such that the thickness of the resulting gate electrode is approximately equal to the thickness of the first polysilicon layer and of the field oxide layer. This results in a surface with minimum topology, which offers an optimum precondition for structuring the gate electrode. In addition, when the gate electrode is etched, the thickness of polysilicon in the active areas is constant everywhere so that overetching can be minimized, resulting in higher process reliability.
In a preferred development of the method according to the invention, the gate oxide is produced by thermal oxidation. Thermal oxidation of a planar, unstructured semiconductor surface at the start of the method permits a thin gate oxide with a high level of quality to be produced, since the semiconductor surface has a low defect density and is particularly planar at the start of the process.
The polysilicon layer lying above the gate oxide layer is preferably produced with a thickness of 50 to 300 nm. Generally, it is desirable to keep the layer as thin as possible. However, on the other hand, it is necessary to ensure that the field plates are sufficiently thick.
Preferab
Kerber Martin
Schwalke Udo
Greenberg Laurence A.
Infineon - Technologies AG
Lee Eddie C.
Lerner Herbert L.
Stemer Werner H.
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