Semiconductor structure and method

Details Semiconductor structure and method Semiconductor structure and method

2006-06-28

2008-12-23

Prenty, Mark (Department: 2822)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S434000

Reexamination Certificate

active

07468307

ABSTRACT:
A semiconductor structure includes a semiconductor layer stack includes a semiconductor substrate of a first conductivity type, a heavily-doped buried layer of a second conductivity type, and a monocrystalline semiconductor layer of a third conductivity type formed on top of the semiconductor layer and the buried layer, a contact to the buried layer, the contact formed in a contact hole, and a lateral insulation of different portions of the semiconductor structure, the insulation formed in an isolation trench. A contact to the semiconductor substrate may be formed within the isolation trench.

REFERENCES:
patent: 4320411 (1982-03-01), Fukushima
patent: 4688069 (1987-08-01), Joy et al.
patent: 4733287 (1988-03-01), Bower
patent: 4745081 (1988-05-01), Beyer et al.
patent: 4792834 (1988-12-01), Uchida
patent: 4910572 (1990-03-01), Kameyama
patent: 4980747 (1990-12-01), Hutter et al.
patent: 5021852 (1991-06-01), Sukegawa et al.
patent: 5614750 (1997-03-01), Ellul et al.
patent: 6114768 (2000-09-01), Gaul et al.
patent: 6121102 (2000-09-01), Norstrom et al.
patent: 2008/0012090 (2008-01-01), Meiser et al.
patent: 0112489 (1984-07-01), None
patent: 0499403 (1992-08-01), None
patent: 1353368 (2003-10-01), None
patent: 63-24672 (1988-02-01), None
patent: 63024672 (1988-02-01), None
German Office Action for German Application No. 10 2006 029 682.6 mailed on Mar. 27, 2008 (9 pages).
De Pestel, F. et al., “Deep Trench Isolation for a 50V 0.35 um Based Smart Power Technology,” IEEE, pp. 191-194 (2003).

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