Metal treatment – Stock – Ferrous
Patent
1986-02-25
1987-06-30
Larkins, William D.
Metal treatment
Stock
Ferrous
357 20, 357 34, 357 55, 357 60, 148DIG10, 148DIG51, 148DIG85, 148DIG117, 148DIG124, 148DIG145, H01L 2704, H01L 2906
Patent
active
046774564
ABSTRACT:
A semiconductor structure is provided by forming an isolation region in a portion of a semiconductor layer, forming a doped region in the semiconductor layer adjacent the isolation region, such doped region having a conductivity type opposite the conductivity type of the semiconductor layer, selectively masking a surface of the semiconductor layer exposing a portion of the doped region adjacent to the isolation region, and selectively etching the exposed portions of the adjacent doped region forming a depression having converging side walls separated from the isolation region by portions of the doped region. The semiconductor layer is an epitaxial layer providing the collector region of a transistor. The bottom portion of the depression is lightly doped to provide an active base region for the transistor. The active base region is electrically connected to the base contact through the more heavily doped region formed in the semiconductor layer. A doped polycrystalline silicon layer is formed over the bottom portion of the depression in contact with the active base region to provide an emitter contact for the transistor.
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patent: 3878552 (1975-04-01), Rogers
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patent: 4168999 (1979-09-01), Vora
IEEE Trans. Electron Dev., vol. ED 25, No. 10, Oct. 1978, p. 1237.
Devlin Peter J.
Larkins William D.
Raytheon Company
Sharkansky Richard M.
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