1975-09-22
1977-09-06
Wojciechowicz, Edward J.
357 43, 357 48, 357 49, 357 50, H01L 2906, H01L 2704, H01L 2712, H01L 2702
Patent
active
040471950
ABSTRACT:
Semiconductor structure having a plurality of isolated islands in which semiconductor devices are formed and which are interconnected to form an integrated circuit. The islands are isolated from each other by a combination of dielectric isolation in the form of moats and regions of higher conductivity extending downwardly into the semiconductor body from the moats. The semiconductor body from which the semiconductor structure is formed has a surface with a <100> orientation. An etch resistant mask is formed on the surface. An anisotropic etch is utilized to provide a plurality of isolation moats extending downwardly from the surface and having inclined side walls oriented along a crystal plane different from the <100> plane and having bottom walls oriented along the <100> crystal plane of the semiconductor body. The side walls and the bottom walls of the moats are oxidized. The oxide on the bottom walls is then removed. Impurities are then caused to enter through the bottom walls to form regions of increased impurity concentration extending down from the bottom walls. Oxide is regrown on the bottom walls and the moats are filled. Devices forming parts of integrated circuits are formed in the islands. The devices are interconnected by leads extending over the moats.
REFERENCES:
patent: 3386865 (1968-06-01), Doo
patent: 3623218 (1971-11-01), Mitarai et al.
patent: 3659160 (1972-04-01), Sloan et al.
patent: 3755001 (1973-08-01), Kooi et al.
Scientific Micro Systems, Inc.
Wojciechowicz Edward J.
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