Semiconductor storing device for reading out or writing data...

Details Semiconductor storing device for reading out or writing data... Semiconductor storing device for reading out or writing data...

2002-10-16

2004-03-16

Tran, Michael (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060

Reexamination Certificate

active

06707750

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storing device for reading out or writing data corresponding to a bit width of a memory cell array from/in a plurality of memory cells of the memory cell array.
2. Description of Related Art
FIG. 9
is a block diagram showing the configuration of a conventional semiconductor storing device. In
FIG. 9
,
101
indicates a conventional semiconductor storing device.
102
indicates a memory cell array in which a plurality of memory cells
103
are disposed in a matrix of 8 rows and 64 columns.
104
indicates each of a plurality of word lines. Each word line
104
is connected with the memory cells
103
placed in the same row. The number of word lines
104
disposed in the conventional semiconductor storing device
101
is equal to eight, and each word line
104
is connected with the sixty-four memory cells
103
.
105
indicates each of a plurality of bit lines. Each bit line
105
is connected with the memory cells
103
placed in the same column. The number of bit lines
105
disposed in the conventional semiconductor storing device
101
is equal to sixty-four, and each bit line
105
is connected with the eight memory cells
103
.
106
indicates a bit selector array.
107
indicates each of a plurality of bit selectors. The bit selector arrays
107
are disposed in the bit selector array
106
, the number of bit selector arrays
107
is equal to thirty-two, and each bit selector
107
corresponds to the memory cells
103
of two columns adjacent to each other. Therefore, each bit selector
107
is connected with two bit lines
105
, and one of the two bit lines
105
is selected in the bit selector
107
according to a signal transmitted through a bit select line
108
. Data-N denoting one-bit data (“0” or “1”) represents each of data-
0
, data-
1
, data-
2
, . . . , and data-
31
, and the one-bit data-N is input to or output from each bit selector
107
. In other words, the memory cell array
102
has a bit width of 32 bits, and 32-bit data is read out or written from/in the thirty-two memory cells
103
of the memory cell array
102
every read or write operation.
108
indicates each of two bit select lines. Each bit select line
108
is connected with the thirty-two bit selectors
107
. In
FIG. 9
, only one bit select line
108
is shown for convenience. The bit select lines
108
relate to two bit lines
105
in one-to-one correspondence in the bit selectors
107
.
109
indicates a row address decoder connected with one end of each word line
104
. A row address signal included in an address signal is input from the outside to the row address decoder
109
, and one word line
104
is selected in the row address decoder
109
according to the row address signal.
110
indicates a column address decoder connected with one end of each bit select line
108
. A column address signal included in the address signal is input from the outside to the column address decoder
110
, and one bit select line
108
is selected in the column address decoder
110
according to the column address signal.
FIG. 10
is a view showing a first addressing arrangement in which addresses are assigned to the memory cells
103
of the memory cell array
102
, and
FIG. 11
is a view showing a second addressing arrangement in which addresses are assigned to the memory cells
103
of the memory cell array
102
. In FIG.
10
and
FIG. 11
, the sixteen addresses ranging from “00” to “3F” are assigned to the memory cells
103
in the memory cell array
102
, and each address is composed of eight bits corresponding to eight memory cells
103
. As an example, “1A.2” denotes the second bit of the address “1A”. In the examples of the address assignment shown in FIG.
10
and
FIG. 11
, each bit selector
106
is connected with two bit lines
105
. However, the number of bit lines connected with each bit selector
106
is arbitrary.
In the first addressing arrangement shown in
FIG. 10
, a group of addresses assigned to one group of memory cells
103
of the bit lines
105
corresponding to each bit select line
108
in each row are increased with the change of the group of memory cells
103
in a row direction (or a right direction in FIG.
10
). For example, one group of addresses “00”, “01”, “02” and “03” assigned to the group of memory cells
103
of the bit lines
105
(placed on the left side in each of the bit selectors
106
) corresponding to one bit select line
108
in the first row (or the top row in
FIG. 10
) are increased to another group of addresses “20”, “21”, “22” and “23” assigned to the group of memory cells
103
of the bit lines
105
(placed on the right side in the bit selectors
106
) corresponding to the other bit select line
108
in the first row. Also, the address is consecutively increased in the row direction in each group of memory cells
103
for each row. For example, the addresses “00”, “01”, “02” and “03” of the group arranged in that order in the first row are increased in the row direction. Also, the addresses of consecutive numbers are assigned to the memory cells
103
connected with the bit lines
105
corresponding to each bit select line
108
. For example, the addresses “00” to “1F” of consecutive numbers are assigned to the memory cells
103
connected with the bit lines
105
(placed on the left side in each of the bit selectors
106
) corresponding to one bit select line
108
.
In the second addressing arrangement shown in
FIG. 11
, a group of addresses assigned to one group of memory cells
103
of the bit lines
105
corresponding to each bit select line
108
in each row are increased with the change of the group of memory cells
103
in the row direction. For example, one group of addresses “00”, “01”, “02” and “03” assigned to the group of memory cells
113
of the bit lines
105
(placed on the left side in each of the bit selectors
106
) corresponding to one bit select line
108
in the first row are increased to another group of addresses “04”, “05”, “06” and “07” assigned to the group of memory cells
103
of the bit lines
105
(placed on the right side in the bit selectors
106
) corresponding to the other bit select line
108
in the first row. Also, the address is consecutively increased in the row direction in each group of memory cells
103
for each row. For example, the addresses “00”, “01”, “02” and “03” of the group arranged in that order in the first row are increased in the row direction. Also, the addresses of consecutive numbers are assigned to the memory cells
103
of each row. For example, the addresses “00” to “07” of consecutive numbers are assigned to the memory cells
103
of the first row.
In case of the first addressing arrangement shown in
FIG. 10
, three lower bits (A
2
, A
1
, A
0
) of the address signal (A
3
, A
2
, A
1
, A
0
) sent from the outside are input to the row address decoder
109
as a row address signal, and the top bit (A
3
) of the address signal is input to the column address decoder
110
as a column address signal. In contrast, in case of the second addressing arrangement shown in
FIG. 11
, three upper bits (A
3
, A
2
, A
1
) of the address signal (A
3
, A
2
, A
1
, A
0
) sent from the outside are input to the row address decoder
109
as a row address signal, and the bottom bit (A
0
) of the address signal is input to the column address decoder
110
as a column address signal.
Next, an operation of the conventional semiconductor storing device
101
, in which the addresses “00” to “3F” are assigned to the memory cells
103
according to the first addressing arrangement shown in
FIG. 10
, will be described below.
In cases where thirty-two pieces of one-bit data corresponding to the 32-bit width of the memory cell array
102
are read out from or written in thirty-two memory cells
103
placed at addresses ranging from the first address “00” to the fourth address “03” as 32-bit data, the first word line
104
placed at the top position is selected in the row address decoder
109
, and the first bit s

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