Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2002-05-30
2004-03-23
Lam, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S194000, C365S229000, C327S158000, C327S163000
Reexamination Certificate
active
06711090
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a high-speed operating semiconductor storage unit (or device) having internal circuits operating in synchronization with an external clock.
More particularly, the invention is directed to a semiconductor storage unit producing two or more data in a cycle of the external clock so as to reduce the power consumption resulting from the supply of the external clock.
Along with the recent tendency toward a higher-speed CPU (Central Processing Unit), the rate of the clock cycle used in memories such as an SDRAM (Synchronous Dynamic RAM) has become higher, and the delay time relative to the clock cycle has become larger. This is now affecting a circuit operation.
As a result, it is the usual practice to avoid a delay relative to external clock by conducting phase control including control of a delay in input buffers and output buffers by means of PLL, and align the phase of internal clock relative to the entered external clock.
In order to improve the rate of reading and writing data in the memory, a process known as the double data rate (DDR) method has been conceived, which comprises transferring data upon startup and end of the clock cycle, and a transfer rate substantially twice as high clock cycle has been achieved.
However, when an output clock of DDR is generated by the use of an existing PLL circuit shown in
FIG. 1
, many clock cycle is required before elimination of a phase difference between an external clock signal and an output clock, and the power consumption becomes larger in the cause of a high-speed clock.
More specifically, a phase comparator
80
divides a VCO
82
output amplified by means of an AMP.
40
into an internal clock CKi by use of a dividing circuit
87
, compares a signal delayed by a delay circuit
88
and an external clock CKo entered from an input circuit
101
via a terminal
100
, and issues or produces a phase error signal &Dgr;ck.
A voltage controlling oscillator
82
generates an internal clock CKi having a frequency corresponding to the phase error signal &Dgr;ck entered via a low-pass filter
81
, and supplies the same to the internal circuit
90
.
By adopting a configuration of the dividing circuit
87
in which a frequency corresponding to a half the entered frequency, the voltage controlling oscillator
82
generates an internal clock CKi with a frequency twice as high as the external clock CKo.
By combining the PLL circuit with the dividing circuit, it is possible to obtain an internal clock CKi for double rates having a phase difference of 180°. However, before elimination of the phase difference between the output clock CKi and external clock signal CKo, the PLL requires input of many external clocks CKo, and the resultant increase in number of clock cycles leads to an increase in power consumption.
To solve such inconvenience, a delay circuit train has been developed as an improved PLL circuit, which permits accurate positional alignment at a higher rate and with a smaller number of clocks and achievement of a lower power consumption, using an SMD (Synchronous Mirror Delay) circuit and a BDD (Bi-Directional Delay). as disclosed in Japanese Unexamined Patent Publications Nos. 8-237091 and 11-066854.
In the BDD circuit and the SMD circuit, the delay portion is turned up, an error in the propagation time caused by fluctuations in the manufacturing process, in the forward period and in the backward period is offset. These delay circuits free from dispersions in timing even upon a change in the cycle time compose the delay circuit train including replica circuits (or dummy circuits) of input and output buffers. This delay circuit train suffices to have only two cycles for elimination of phase differences.
In the above-mentioned existing art, however, while it is possible to cause the phase of output data to cope with a higher rate relative to the external clock, stop control of the SMD circuit and the BDD circuit is not carried out during active power down because of the restriction imposed by the CAS latency.
Herein, it is to be noted that the term “active power down” as used herein means a state in which, after input of an active command (ACT) which activates a low-address of a bank selected by an address, supply of the internal clock to outside the delay circuit train including the SMD circuit or the BDD circuit is discontinued, bringing the clock enable signal into a disable state.
A BDD signal generating circuit (delay circuit train) including a BDD circuit in an existing semiconductor storage unit is illustrated in FIG.
2
.
In such a BDD signal generating circuit, delay lines
17
,
18
,
19
and
20
generate BDD signals (output clocks) of phase A, phase B, phase C and phase D, respectively, having a phase shift of 90° to two cycles of the output clock signal, i.e., the external clock signal, used for data output based on the DDR method through control of BDD selecting circuits
11
and
12
.
When stopping operation for saving power, an existing BDD signal generating circuit has a configuration in which by stopping a CLK first-stage circuit
1
and a CLKB first-stage circuit
2
, supply of the external clock is discontinued to the subsequent circuits.
When the clock first-stage enable signal is brought into the disable condition, and the CLK first-stage circuits
1
and
2
are stopped, during active power down for the purpose of saving power, two cycle of external clock are required for generating a BDD signal. Upon returning to the active state, therefore, it is impossible to generate BDD signals corresponding to values of CAS latency (particularly, CAS latency of 2.0 or 1.5) from the read command (READ).
As is understood from the timing chart of an existing method illustrated in
FIG. 3
, therefore, the clock first-stage enable signals supplied, respectively, to the CLK first-stage circuit
1
and the CLKB first-stage circuit
2
are not in the disable state, but in the enable state (negative logic) even during active power down.
As described above, the existing BDD signal generating circuit, which operates even during active power down by means of a high-speed clock, has a problem of an excessive power consumption in spite of the power-down state.
SUMMARY OF THE INVENTION
It is therefore an object of this invention to provide a semiconductor storage unit which generates a control signal controlling power down in a BDD signal generating circuit during active power down to match with a value of CAS latency and applying power-down control to each of delay circuit trains including a BDD circuit (or SMD circuit), thereby permitting reduction of power consumption during active power down.
The semiconductor storage unit of the present invention comprises a clock input first-stage circuit for input of an external clock signal; an output circuit issuing data stored in memory cells in synchronization with an output clock generated on the basis of the external clock signal; a delay adjusting circuit composed of a plurality of delay circuits, which corrects a phase shift between the external clock and a data output by delaying the output clock and achieves synchronization between the external clock signal and the data; and a control circuit which controls operation and stoppage for each of the plurality of delay circuits.
In the semiconductor storage unit of the invention, the control circuit controls operations of each of the plurality of delay circuits on the basis of CAS latency during active power down.
In the semiconductor storage unit of the invention, the control circuit controls which of the plurality of delay circuits is to be operated or stopped, on the basis of the value of CAS latency.
In the semiconductor storage unit of the invention, the delay adjusting circuit comprises replica circuits including the clock input first-stage circuit and the output circuit, and an adjusting delay circuit which adjusts propagation to an arbitrary amount of delay.
In the semiconductor storage unit of the invention, the adjusting delay circuit adjusts the amount of delay by turning up pr
Choate Hall & Stewart
Lam David
NEC Corporation
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