Semiconductor storage unit

Details Semiconductor storage unit Semiconductor storage unit

1999-11-19

2001-10-16

Hoang, Huan (Department: 2818)

Static information storage and retrieval

Addressing

Plural blocks or banks

C365S230060, C365S051000, C365S063000

Reexamination Certificate

active

06304509

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage unit and in particular to a semiconductor storage unit with a plurality of banks.
2. Description of the Prior Art
FIG. 33
shows one example of electric configuration of the conventional semiconductor storage unit disclosed in Japanese Patent Application No. 9-305505, where (a) and (b) are a block diagram showing the electric configuration of the main part and a circuit diagram showing a configurational example of a circuit provided inside the block diagram shown in FIG.
33
(
a
), respectively.
As shown in FIG.
33
(
a
), the semiconductor storage unit of this example comprises two banks
2
a
and
2
b
with a plurality of subarrays
1
,
1
, . . . arranged in a matrix form. The banks
2
a
and
2
b
each comprise: the respective sense amplifier columns (SA)
3
,
3
, . . . and the respective subword driver columns (SWD)
4
,
4
, . . . for individual subarrays
1
,
1
, . . . the respective subword lines (SWL)
5
,
5
, . . . wired in the X direction (horizontal direction in the figure) of a subarray
1
for individual subarrays
1
,
1
, . . . ; and the respective bit lines (BL)
6
,
6
, . . . wired in the Y direction (vertical direction in the figure) of a subarray
1
for individual subarrays
1
,
1
, . . . ; the respective local I/O lines (LIO)
7
,
7
, . . . and the respective main word lies (MWL)
8
,
8
, . . . wired in the X direction of a subarray
1
; and the respective column selection line (CSL)
9
,
9
, . . . wired in the Y direction of a subarray
1
for individual subarrays
1
,
1
, . . . .
Besides, provided in common to the banks
2
a
and
2
b
are global I/O lines (GIO)
11
connected to I/O amplifiers
10
0
and
10
1
, comprising write amplifiers, data amplifier or the like in the Y direction of subarray
1
, controlled by a logical sum of signals conveyed over a column selection line
9
, and switch lines (SWIO)
12
which is wired in the same direction as the global I/O lines
11
with one for each arranging column of the global I/O lines
11
and along which signals RWSRj indicating the active state of columns for connecting local I/O lines
7
and global I/O lines
11
are conveyed.
Next, the operation of the semiconductor storage unit configured above will be described. First, when the bank
2
a
is selected in accordance with a signal RACTj conveyed over the signal line
13
for indicating the active state of the row, a main word line
8
and a sub-word line
5
provided on the bank
2
a
are activated and moreover a signal SE for activating the sense amplifier column
3
stands up. When a sub-word line
5
is activated, bit lines
6
connected to the sub-word line
5
are gradually activated. Besides, activation of the sense amplifier column
3
by the signal SE causes the leading of a signal SAP.
Next, at the same time when a column selection line
9
provided on any subarray
1
is activated, a switch line
12
for connecting a local I/O line
7
and a global I/O line
11
provided on the subarray
1
is activated. Thereby, the local I/O line
7
and the global I/O line
11
provided on the subarray
1
are connected, both of them are gradually activated, and the data written in the memory cell
14
present on a bit line
6
of a desired subarray
1
in the bank
2
a
are read out.
Thereafter, when the column selection line
9
and the switch line
12
in the bank
2
a
becomes inactive and a column selection line
9
and a switch line
12
in the bank
2
b
are activated instead, a local I/O line
7
and a global I/O line
11
provided on the subarray
1
in the bank
2
b
are connected, both of them are gradually activated, and the data written in the memory cell
14
present on a bit line
6
of a desired subarray
1
in the bank
2
b
are read out.
Incidentally, the operation till the column selection line
9
and the switch line
12
in the bank
2
b
are activated will be omitted, because of being almost similar to that in the bank
2
a.
BRIEF SUMMARY OF THE INVENTION
Object of the Invention
Meanwhile, in the above conventional semiconductor unit, indeed since global I/O lines
11
are provided in common to the banks
2
a
and
2
b
and moreover switch lines
12
are wired with one for each arranging column of the global I/O lines
11
in the same direction as the global I/O lines
11
, the number of wiring lines can be reduced and the chip area can be minimized as compared with a case where they are provided respectively for individual banks or for individual subarrays.
In the conventional semiconductor unit, however, since the number of signal lines for conveying the signal of an I/O amplifier
10
or signal lines for conveying the signal for activating a column decoder (YDEC in
FIG. 33
) or the like cannot be reduced, there was a limit to the reduction of the chip area in the semiconductor storage unit.
Besides, in the above semiconductor storage unit, since global I/O lines
11
are provided in common to the banks
2
a
and
2
b
, the time taken to convey data on a global I/O line
11
lengthens as compared with a case where I/O lines are provided respectively for individual banks. Accordingly, considering the delay of data on a global I/O line
11
, a column decoder or an I/O amplifier must be activated, but no account whatever is made of this point in the conventional semiconductor storage unit. For this reason, with the connecting configuration of the I/O amplifier
100
and the I/O amplifier
10
, to a common data I/O bus, for example, there is a fear that data read out from the respective banks
2
might collide with each other on a data I/O bus in a continuous readout of data from the banks
2
a
and
2
b.
Furthermore, in the above conventional semiconductor storage unit, a local I/O line
7
and a global I/O line
11
are connected in accordance with a signal RWS
j
conveyed on the switch line
12
, but no generation circuit for generating a signal RWS
j
is disclosed. Thus, there was a disadvantage in that switching for selecting the connection to a local I/O line
7
and the connection to a global I/O line
11
cannot be concretely implemented without any damage to data read from the banks
2
a
and
2
b
or data written into the banks
2
a
and
2
b.
Besides, Japanese Patent Application No. 9-305505 describes that short-circuiting a global I/O line
11
during the switching period between the control over the bank
2
a
and the control over the bank
2
b
shortens the time until the subsequent operation begins, but discloses no specific circuits whatever. Thus, there was a disadvantage in that no speedup of operation in the switching time mentioned above is specifically implementable.
Besides, in a large capacity semiconductor storage unit, the test mode in which data are written into a plurality of bank at a time or read out at a time is provided to shorten the time for a fault analysis or an estimating test and there are cases where a test signal for this mode is supplied to the semiconductor storage unit. In the case of a global I/O lines
11
provided in common to the upper and lower banks
2
a
and
2
b
like the above conventional semiconductor storage unit, there was another demerit that supplying a test signal as it is allows data read out from individual banks
2
a
and
2
b
and conveyed to collide with each other in the global I/O line
11
, thereby disabling the test to be normally carried out because the upper and lower buses are simultaneously activated.
Fulfilled in consideration of these circumstances, the present invention has an object in providing a semiconductor storage unit enabling the number of wiring lines to be reduced as well as the collision of data on data I/O buses to be prevented and capable of switching the connection between a local I/O line and a global I/O line without occurrence of damages to data, implementing speedup of the operation in the switching time of control for upper and lower banks and further performing a test normally and in a short time about fault analysis o

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