Semiconductor storage device with improved layout of power suppl

Details Semiconductor storage device with improved layout of power suppl Semiconductor storage device with improved layout of power suppl

1996-05-20

1999-02-02

Nelms, David

Static information storage and retrieval

Powering

365 51, 365 63, G11C 700

Patent

active

058674403

ABSTRACT:
A memory cell array includes a plurality of memory cells that are arranged in the row and column directions. Power supply lines and grounding lines are arranged on the memory cell array so as to extend in the column direction. The grounding lines are so arrayed that a plurality of power supply lines are interposed therebetween or, conversely, the power supply lines are so arranged that a plurality of grounding lines are interposed therebetween. By connecting together adjacent power supply lines (or grounding lines) of the same potential on a column decoder to form a single power line, the number of power supply lines extending in the column direction on the column decoder can be reduced, whereby an effective element forming region of the column decoder can be expanded.

REFERENCES:
patent: 5231607 (1993-07-01), Yoshida et al.
patent: 5293559 (1994-03-01), Kim et al.
patent: 5321646 (1994-06-01), Tomishima et al.
patent: 5325336 (1994-06-01), Tomishima et al.

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