Static information storage and retrieval – Interconnection arrangements – Transistors or diodes
Reexamination Certificate
2011-01-11
2011-01-11
Tran, Andrew Q (Department: 2824)
Static information storage and retrieval
Interconnection arrangements
Transistors or diodes
C365S063000, C365S051000, C365S206000
Reexamination Certificate
active
07869245
ABSTRACT:
An excess region on a chip plane is eliminated to reduce a chip size. A plurality of data pads, which input/output data, are arranged near one side of an outer periphery of a substrate in parallel with the aforementioned one side, and a plurality of data pads, which input/output data, are arranged on an inner side of the plurality of data pads in parallel with the plurality of data pads. NMOSs, which output data, are arranged between the data pads, and PMOSs, which output data, are arranged at positions where they face the NMOSs near the data pads.
REFERENCES:
patent: 7158397 (2007-01-01), Rinerson et al.
patent: 7307871 (2007-12-01), Liaw
patent: 2004/0141352 (2004-07-01), Dufourt et al.
patent: 07-202145 (1995-08-01), None
patent: 08-017965 (1996-01-01), None
patent: 08-316436 (1996-11-01), None
Oki Semiconductor Co., Ltd.
Studebaker Donald R.
Studebaker & Brackett PC
Tran Andrew Q
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