Semiconductor storage device provided with memory cell...

Details Semiconductor storage device provided with memory cell... Semiconductor storage device provided with memory cell...

2009-02-04

2010-10-19

Phung, Ahn K. (Department: 2824)

Static information storage and retrieval

Floating gate

Multiple values

C365S185240

Reexamination Certificate

active

07817468

ABSTRACT:
A semiconductor memory device includes memory cell transistors, a first selection transistor, and word lines. Each of the memory cell transistors has a stacked gate including a charge accumulation layer and a control gate, and is configured to retain at least two levels of “0” data and “1” data according to a threshold voltage. The threshold voltage corresponding to the “0” data being the lowest threshold voltage in the levels retained by each of the memory cell transistors. The first selection transistor has a current path connected in series to one of the memory cell transistors. Each of the word lines is connected to the control gate of one of the memory cell transistors. upper limit values of threshold voltages of the memory cell transistors retaining the “0” data being different from one another in each word line.

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