Static information storage and retrieval – Addressing – Particular decoder or driver circuit
Reexamination Certificate
1999-12-16
2001-03-27
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Particular decoder or driver circuit
C365S230080, C365S233100
Reexamination Certificate
active
06208580
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor storage devices such as synchronous dynamic random-access memories.
This application is based on Patent Application No. Hei 10-368193 filed in Japan, the content of which is incorporated herein by reference.
2. Description of the Related Art
In the semiconductor storage devices such as synchronous dynamic random-access memories (i.e., synchronous DRAMs), memory cells each storing a single bit, which is a minimum unit of data, are arranged in a matrix form and are connected together using word lines and bit lines. Herein, the bit lines are arbitrarily selected after the word lines are activated based on address signals given from the external (i.e., external device or system), so that read/write operations of data are performed on the memory cells by way of the selected bit lines.
Next, an example of a configuration of the conventional semiconductor storage device will be described by giving attention to the bit line(s) being selected.
Now, a basic configuration of the semiconductor storage device will be described with reference to
FIG. 2
, details of which will be described later.
In
FIG. 2
, memory cells “MC” are arranged in a memory cell array, wherein word lines “WL” are laid in directions of rows, while bit lines “BL” are laid in directions of columns. So, each memory cell MC is connected between the corresponding word line and bit line. To avoid an event in which the memory cells respectively connected to adjoining bit lines are simultaneously selected, each of the word lines is connected only with the memory cells, which belong to an odd-numbered column or an even-numbered column in the memory cell array consisting of rows and columns.
In addition, a single sense amplifier “SA” (e.g., SA
0
) is provided for two adjoining bit lines “BL” (e.g., BL
0
and BL
1
). Herein, the sense amplifier SA is of a latch type, which is configured mainly by a flip-flop circuit. The sense amplifier is activated at a predetermined timing to sense (or latch) and amplify a weak data signal, which is given from the memory cell MC on the bit line BL.
Each of the bit lines BL is connected to a data line DB (i.e., DBa, DBb) by way of a column selecting transistor T (i.e., T
01
to T
32
). Herein, a pair of bit lines connected to a same sense amplifier are connected to two data lines by two column selecting transistors respectively. Each column selecting transistor is turned on by a column selecting signal YS (i.e., YS
01
-YS
04
) so that each bit line is connected to the corresponding data line.
The data lines are connected to a data amplifier
410
. The data amplifier
410
amplifies the data signal of the memory cell MC which appears on the data line. In the example of
FIG. 2
, eight bit lines BL
0
to BL
7
are collectively connected to the data amplifier
410
as one unit, which is repeated in the memory cell array. So, 512 bit lines are provided in the memory cell array in total.
FIG. 11
shows an example of a decoder circuit, which is conventionally used to produce the aforementioned column selecting signals by decoding column address signals being input from the external. In
FIG. 11
, column pre-decoders
321
A to
323
A perform pre-decoding on column address signals YA
0
to YA
8
, which are input thereto by way of an address buffer circuit (not shown). Herein, each pre-decoder is activated to operate by a buffering signal &phgr;
0
.
A column decoder
330
A decodes output signals of the column pre-decoders
321
A to
323
A to produce column selecting signals YS
01
to YS
04
, which are used to control conductions of the column selecting transistors. There are provided sixty-four column decoders in total. Each column decoder (
330
A) is configured to specify any one of the column selecting signals YS
01
to YS
04
in response to the output signals of the column pre-decoder
321
A. So, only one of the sixty-four column decoders is activated in response to the output signals of the column pre-decoders
322
A and
323
A.
Namely, the decoder circuit of
FIG. 11
outputs 256 column selecting signals in total. Herein, only one of the column selecting signals is activated in response to the column address signal given from the external. There are provided two sets of the decoder circuit shown in
FIG. 11
, which output 512 column selecting signals in total. Each set is selected by the address signal YA
8
. Then, one of the 512 column selecting signals is selected at last.
In the aforementioned semiconductor storage device, the column selecting signals “YS” (i.e., YS
01
-YS
04
) output from the column decoder
330
A make transition in synchronization with the column address signals input to the column pre-decoders
321
A to
323
A. Herein, each column selecting signal selects a pair of bit lines by controlling conductions of the column selecting transistors.
In order to minimize time lags (or deviations) in timing between column address signals due to wiring load, the conventional semiconductor storage device is designed such that the address buffer circuits are arranged on a chip in a concentrated manner, so that lengths of wires laid between the address buffer circuits and column pre-decoders are adjusted to be substantially identical to each other. To cope with increasing capacities of memories, it is necessary to reduce wiring areas as minimally as possible. In order to do so, wires used for the column address signals of the address buffer circuits are formed as groups, which are arranged adjacent to each other.
If the wires used for the column address signals are arranged to be adjacent to each other, a coupling capacity (or coupling capacitor) is formed between the wires. So, crosstalk is caused to occur between the wires due to the coupling capacity. In addition, a time lag is caused to occur in timing between the column address signals being input to the column pre-decoders, so that a time lag is correspondingly caused to occur in timing between the column selecting signals being output from the column decoder. This may cause a multiple selection of bit lines in which multiple (pairs of) bit lines are simultaneously selected.
Next, a description will be given with respect to a mechanism in which a time lag is caused to occur in timing between the column address signals due to the coupling capacity being formed between the wires. Herein, the description will be given concretely with attention to two adjoining wires. Suppose that column address signals on the two adjoining wires make level transition in a same direction, in which both of the column address signal change in level from L level (or low level) to H level (or high level) or from H level to L level. In that case, an electric potential difference is retained substantially constant between terminals of the coupling capacity being formed between the wires. So, there is almost no probability in which the coupling capacity is charged or discharged due to level transition of the column address signals. Therefore, the coupling capacity does not become apparent, so the column address signals on the wires are transmitted at a high speed without being influenced by the coupling capacity.
In contrast, if the column address signals on the two adjoining wires make level transition in different directions respectively, or if only one of the column address signals makes level transition, the coupling capacity must be charged or discharged, so that the coupling capacity becomes apparent. In that case, the column address signals on the wires are influenced by the coupling capacity, so time lags are caused to occur in timing between the column address signals as shown in FIG.
12
A. Due to such time lags between the column address signals, time lags as show in
FIG. 12B
are correspondingly caused to occur in timing between output signals (or column selecting signals) of the column pre-decoders, which make transition in synchronization with the column address signals.
In
FIG. 12A
, reference symbols YFD, YFU show waveforms, which are related to a “h
NEC Corporation
Nelms David
Sughrue Mion Zinn Macpeak & Seas, PLLC
Yoha Connie C.
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