Semiconductor storage device having latch circuitry coupled to d

Details Semiconductor storage device having latch circuitry coupled to d Semiconductor storage device having latch circuitry coupled to d

1994-05-03

1996-05-14

Nelms, David C.

Static information storage and retrieval

Addressing

Sync/clocking

36518905, 36523003, 36518901, G11C 800

Patent

active

055174612

ABSTRACT:
A semiconductor storage device includes a plurality of memory cells, a selecting circuit for selecting, in accordance with address information supplied from an external unit, a memory cell from among the plurality of memory cells, there being a case where a memory cell identified by the address information supplied from the external unit is not present in the plurality of memory cells, a data line to which the plurality of memory cells are coupled, data read out from the selected memory cell being transmitted through the data line, the data line being able to be in a floating state when a memory cell identified by address information is not present in the plurality of memory cells, an amplifier for amplifying the data transmitted through the data line, a latching circuit for latching a potential level of data which has been supplied to the data line, and a control circuit for controlling the latching circuit so that the latching circuit is inactive in a predetermined period including a time at which the data line receives data read out from the memory cell.

REFERENCES:
patent: 4611299 (1986-09-01), Hori et al.
patent: 4995002 (1991-02-01), Yamada et al.
patent: 5043944 (1991-08-01), Nakamura et al.
patent: 5146427 (1992-09-01), Sasaki et al.
patent: 5257226 (1993-10-01), McClure
patent: 5260903 (1993-11-01), Suyama et al.

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