Semiconductor storage device having address-transition detecting

Details Semiconductor storage device having address-transition detecting Semiconductor storage device having address-transition detecting

1995-08-08

1997-08-12

Nelms, David C.

Static information storage and retrieval

Floating gate

Particular connection

3651852, 3652335, 365194, G11C 1134, G11C 800

Patent

active

056572697

ABSTRACT:
A semiconductor storage device is basically configured similar to a mask ROM which comprises a memory cell array, an address buffer, a row decoder, a column decoder and a sense amplifier circuit. The semiconductor storage device is specifically designed to deal with addresses which are sequentially inputted thereto in synchronization with address cycles without a margin of time. An address-transition detecting circuit is provided to detect an address transition which occurs at a change of the address cycles. A sense-determination detecting circuit detects the sense determination of the sense amplifier circuit on the basis of the address transition so as to produce a control signal. A data latch circuit latches the output of the sense amplifier circuit in accordance with the control signal. The control signal is determined in such a way that the output of the sense amplifier circuit is latched by the data latch circuit in synchronization with the address cycles in turn. Since no margin of time is required by the address cycles, it is possible to perform high-speed read-out operations on the memory cell array. Moreover, the sense-determination detecting circuit uses delay circuits containing dummy cell arrays which are configured similar to the memory cell array, so it is possible to accurately and automatically measure the time which elapses until the sense determination of the sense amplifier circuit.

REFERENCES:
patent: 4800304 (1989-01-01), Takeuchi
patent: 5327394 (1994-07-01), Green et al.
patent: 5457661 (1995-10-01), Tomita et al.

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