Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
1999-05-26
2002-02-19
Tran, Toan (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S024000, C327S174000, C365S233500
Reexamination Certificate
active
06348822
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to an internal synchronization type semiconductor storage device having a standby function, and in particular, to a semiconductor storage device intended for increasing the access speed in gaining access by canceling a standby state.
Conventionally, the standby function of a semiconductor storage device is designed for the purpose of reducing the power consumption in the standby state of the semiconductor storage device. In general, the standby function exists in the semiconductor storage devices such as DRAM (Dynamic Random Access Memory), SRAM (Static RAM) and MROM (Mask Read Only Memory). The standby function is designed so that a signal for designating a standby state for this standby function (it is herein assumed that the signal is a CE signal, which leads to the standby state when the CE signal has H-level and leads to the cancellation of the standby state, i.e., the operating state when the CE signal has L-level) is inputted to an address input circuit or the like of the semiconductor storage device and the address input circuit or the like does not operate even when an address signal is externally inputted. If the address input circuit operates in the standby state, then the internal circuits subsequent to the address input circuit also operate, consequently failing in reducing the power consumption.
Examples of the address input circuit and the CE input circuit are shown in
FIGS. 5A and 5B
. It is hereinafter assumed that the address input circuit and the CE input circuit have the circuit constructions shown in
FIGS. 5A and 5B
. With these circuit constructions, the address signal is transmitted to the internal circuit when the CE signal has L-level, whereas the address signal is not transmitted to the internal circuit when the CE signal has H-level. That is, when the CE signal has H-level, the output signal of the address input circuit is fixed at H-level whatever address signal is inputted, and the internal circuit does not operate. That is, the above state is the standby state.
A CE signal (assumed to be a CEa signal, having the same polarity as that of the CE signal) in the semiconductor storage device, the signal being formed when the aforementioned CE signal is inputted, is inputted to all the address input circuits. These address input circuits are generally laid out in the vicinity of wire bonding pads in order to reduce the chip area of the semiconductor storage device. In this case, the pads are normally arranged along the sides of the chip in connection with the wire bonding. Accordingly, the address input circuits laid out in the vicinity of the pads are also arranged along the sides of the chip. The CEa signal is required to be inputted to the address input circuits arranged along the sides of the chip. If this CEa signal is changed (according to a change of the CE signal), then the signal delay becomes small in the case of the address input circuit arranged near the CE input circuit (CE signal pads) and becomes large in the case of the address input circuit arranged far away from the CE input circuit.
Consideration is now given to the access time when gaining access by canceling the standby state on the basis of the aforementioned circumstances (the access being referred to as a “CE access” hereinafter). With regard to the CE access operation, first, the CE signal that is the signal for canceling the standby state changes from H-level to L-level. This CE signal is inputted to the CE input circuit, and the CEa signal outputted from the CE input circuit also changes from H-level to L-level. This CEa signal is inputted to each address input circuit. Upon receiving the CEa signal as input, each address input circuit cancels the standby state and enters into the normal operating state. From this state, each address input circuit starts its operation similar to the normal access (referred to as an “address access” hereinafter). The access time in the case of the CE access becomes longer than in the case of the address access. This is because each address input circuit operates similarly to the case of the address access after the CEa signal that is the output signal of the CE input circuit is inputted to each address input circuit. That is, the access time becomes longer than in the case of the address access by the time during which the CEa signal is transmitted to each address input circuit. This will be explained in detail below.
Generally, in the semiconductor storage device of the internal synchronization type such as SRAM, an internal operation timing control use reference pulse necessary for the internal circuit is generated by detecting a change of the address signal inputted to the address input circuit. This reference pulse is used for determining the operating timing of principal peripheral circuits, practically in generating a timing signal for reading data from a memory array of which the address is designated or in generating a data output timing signal. The pulse width and timing of this reference pulse generally become one factor for determining the access time. Therefore, this reference pulse should preferably be designed to the pulse width of the necessary minimum length for the internal circuit. This reference pulse is often produced by utilizing a pulse signal generated in a circuit that is generally known as an address transition detection circuit (ATD circuit) or the like. An example of this ATD circuit is shown in FIG.
6
. This circuit is constructed of a delay circuit and an exclusive-OR circuit and operates to generate and output a one-shot pulse signal when the input signal changes. The pulse width of this one-shot pulse signal is adjusted by the delay circuit. The operating waveform of this circuit is shown in
FIGS. 14A-14C
.
The reference pulse generating circuit that utilizes the one-shot pulse signal generated by the ATD circuit generates a reference pulse based on the address change time. After the reference pulse is outputted, specified processing is executed in each circuit to output data. The relations between these signals are shown in
FIGS. 9A-9D
. It is assumed that the horizontal axis represents the time and the vertical axis represents the potential level (H-level or L-level) in such a chart related to timing. A signal PAD_AD represents the address signal to be inputted to the semiconductor storage device. The address input circuit forms an output signal upon receiving this PAD_AD signal, the output signal being assumed to be AD. A time period from this PAD_AD to the output of AD is assumed to be T
3
. The ATD circuit detects a change of the signal AD and generates a one-shot pulse signal. Based on this one-shot pulse signal, the reference pulse necessary for the internal circuit is generated by utilizing a delay circuit that employs an inverter or the like. This signal is assumed to be ADCLK. A time period from the time of change of the signal AD to the rise time of ADCLK is assumed to be T
4
. The ADCLK signal is assumed to be an H-level active signal, and the time period during which this ADCLK signal is at H-level is assumed to be T
5
. The circuit construction is such that the data is outputted after a lapse of a specified time period T
6
from the time at which ADCLK comes to have L-level. The waveform timing of this data output is assumed to be DOUT_AD. The time from decision of the address to the data output becomes the access time, and therefore, Tad is the address access time. That is, Tad=T
3
+T
4
+T
5
+T
6
.
The address change must be detected upon the change of any address terminal, and therefore, this ATD circuit is necessary for each output of each address input circuit. When generating a reference pulse by utilizing the ATD circuit, the reference pulse must be generated upon the change of any address, and therefore, a construction as shown in
FIG. 4
or a construction that functionally conforms to the construction is general. An example of the delay circuit A shown in
FIG. 4
is shown in FIG.
7
. The circuit of
FIG.
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
Tra Quan
Tran Toan
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