Static information storage and retrieval – Floating gate – Particular biasing
Patent
1998-02-19
2000-06-27
Nelms, David
Static information storage and retrieval
Floating gate
Particular biasing
36518525, 36518521, G11C 1606
Patent
active
060814527
ABSTRACT:
A verify operation is accurately collectively executed on all memory cells. In verify operation, first, the levels of a pre-charge signal .phi.pre and a collective erase verify mode selection signal .phi.aev are made to be "L", so that a common bit line 5 and all bit lines BL0 through BLm are individually charged with a pre-charge voltage Vpre. Thereafter, the level of the collective erase verify mode selection signal .phi.aev is made to be "H" to connect the common bit line 5 to all the bit lines BL0 through BLm and a sense amplifier 8, and all word lines WL0 through WLn are selected by a row decoder circuit 2. Then, there is watched an event that the common bit line 5 is discharged and an output signal OUT of the sense amplifier 8 becomes "L" due to the existence of a non-erased memory cell in a memory cell array 1. In this case, the discharge of the common bit line 5 occurs when at least one non-erased memory cell transistor MT exists in the memory cell array 1, and therefore, the verify operation can be accurately collectively executed on all the memory cells.
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Nelms David
Nguyen Van Thu
Sharp Kabushiki Kaisha
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