Static information storage and retrieval – Powering – Conservation of power
Reexamination Certificate
2000-06-01
2002-01-01
Elms, Richard (Department: 2824)
Static information storage and retrieval
Powering
Conservation of power
C365S226000, C365S228000, C365S229000
Reexamination Certificate
active
06335895
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device, such as a DRAM, and a system, such as a memory board, using the semiconductor storage devices.
2. Description of Related Art
Recently, as the degree of integration of a memory (semiconductor chip) such as a DRAM (dynamic random access memory) increases, especially in a memory system such as a memory board comprising a plurality of semiconductor chips, it has become desirable to decrease the power consumption of each memory when in a stand-by state.
In a memory, in order that the memory maintains data when in a stand-by state, at least two kinds of current are necessary. The first is the current to be supplied to a circuit for generating a half VCC (HVCC; which is a half of a source voltage and is shown as HVC in the figures), and the second is the current to be supplied to a circuit for generating a back bias voltage. The voltage HVCC is used to precharge bit lines and is supplied to counter electrodes in memory cells. On the other hand, the back bias is a voltage applied to transistor substrates included in the memory cells, and is generally about −1 volt in the case of DRAMs. Therefore, in a memory system, it is necessary to provide internal power supply circuits (voltage regulators) for generating such kinds of voltage, and to supply currents to each of the internal power supply circuits. Therefore, in order to reduce power consumption of a memory in a stand-by state, it is necessary to reduce the currents to be supplied to those internal power supply circuits.
Japanese Patent Application Laid-open No. Hei 9-063267 titled “Semiconductor Storage Device” discloses an example of a DRAM or a memory board in which power consumption can be reduced. This memory board comprises a plurality of DRAMs having no lowering voltage circuit and a buffer circuit for lowering supply voltage, and the lowered supply voltage is supplied to the external power reception pin of each DRAM. In this memory board, because the lowered supply voltage is supplied to each DRAM as a supply voltage, the power consumption of the internal power supply circuits provided in each DRAM can be reduced.
FIGS. 17
to
19
diagrammatically illustrate an embodiment disclosed in the above prior art document. As shown in
FIG. 17
, a memory board
100
comprises eight DRAMs
110
and a controller
120
which controls the DRAMs
110
. The controller
120
receives external control signals /RAS and /CAS and supplies to the DRAMs row-address strobe signals /RASd and column-address strobe signals /CASd. As shown in
FIG. 18
, the controller
120
includes a buffer circuit
121
, and this buffer circuit
121
lowers the supply voltage VCC to generate a lowered voltage VCL. For example, the supply voltage VCC is 5 volts and the lowered voltage VCL is 3.3 volt, and the lowered voltage VCL is supplied to the DRAMs
110
as a supply voltage.
Furthermore, in this prior art, in order to reduce the supply current when in a stand-by state, as shown in
FIG. 18
, the buffer circuit
121
consists of a pair of buffer amplifiers
121
a
and
121
b
and a state detecting circuit
122
. The buffer amplifiers
121
a
and
121
b
receive a reference voltage VREF as an input voltage. When the DRAMs are in a stand-by state, the state detecting circuit
122
detects a stand-by state of the DRAMs
110
based on signals /RAS and /CAS, and outputs a stand-by signal ACT to a transistor
121
c.
The stand-by signal ACT turns off the transistor
121
c,
and the power supply to the buffer amplifier
121
b
is turned off. In this way, the controller
120
detects, based on signals /RAS and /CAS, that the DRAMs
110
are in a sleep mode, the controller
120
turns off the buffer amplifier
121
b
to reduce the output current of the lowered supply voltage VCL.
FIG. 19
illustrates an internal circuit of each DRAM
110
shown in FIG.
17
. The DRAM
110
comprises an internal power supply circuit
110
a,
a plurality of one-transistor RAM cells (memory cells)
110
b,
and a plurality of sense refresh circuits
110
c.
In
FIG. 19
, only one of the memory cells
110
b
and one of the sense refresh circuits
110
c
are illustrated for the purpose of simplification. The internal power supply circuit
110
a
generates an intermediate voltage HVCC (HVC) from the voltage VCL supplied from the controller
120
. The memory cell
110
b
consists of a n-MOS transistor M
20
and a capacitor C
20
. The sense refresh circuits
110
c
consists of a sense amplifier A
30
, n-MOS transistors M
30
, M
31
, and M
32
.
In the internal power supply circuit
110
a,
a resistor R
10
, n-MOS transistor M
10
, p-MOS transistor M
11
, and a resistor R
11
are connected in series between the lowered supply voltage terminal VCL and a ground GND. The internal power supply circuit
110
a
further comprises an n-MOS transistor M
12
and a p-MOS transistor M
13
. The n-MOS transistor M
12
comprises a drain connected to the terminal VCL, and a gate connected to the gate and drain of the n-MOS transistor M
10
and to one end of the resistor R
10
. The p-MOS transistor M
13
comprises a gate connected to the gate and drain of the p-MOS transistor M
11
and to one end of the resistor R
11
. The sources of the n-MOS transistor M
12
and the p-MOS transistor M
13
are connected to each other, and their junction outputs a HVCC voltage HVC.
In the memory cell
110
b,
n-MOS transistor M
20
has a drain connected to a bit line BL, a gate connected to a word line WL, and a source connected to one terminal of a capacitor C
20
. The other terminal of the capacitor C
20
is connected to the voltage HVC.
In the sense refresh circuit
110
c,
a complimentary pair of bit lines are connected to a sense amplifier A
30
as difference inputs, and gates of three n-MOS transistors M
30
, M
31
, and M
32
are connected to a precharge (BPR) signal line BPR of the bit lines so that refresh control can be performed at data readout times and at predetermined refresh intervals based on the BPR signals. The drains of the n-MOS transistors M
30
and M
32
are respectively connected to the input terminals of the sense amplifier A
30
, and their sources are connected to the voltage HVC. Furthermore, the drain and source of the n-MOS transistor M
31
are connected in parallel to the difference inputs.
As is described above, the DRAMs
110
comprises an internal power supply circuit
110
a
for generating a lowered supply voltage HVC, and the internal power supply circuit supplies pulse currents to a plurality of memory cells in the same memory when refresh operations are performed. Therefore, in order to stabilize the output voltage of the internal power supply circuit, it is desirable to reduce the impedance thereof. For this reason, in the art disclosed in
FIG. 19
, the drains and sources of the transistors M
12
and M
13
are connected in series, and the sources of the transistors M
12
and M
13
are connected to an output terminal. In this configuration, it is easy to reduce the output impedance of the internal power supply circuit without complicating the circuit configuration.
However, in the memory shown in
FIG. 19
, it is necessary to maintain the value of the through current flowing through the transistors M
12
and M
13
at more than a constant value in order to prevent oscillation of the circuit. Therefore, even if the supply voltage of the DRAMs is reduced, or even if a supply current lowering circuit such as shown in
FIG. 18
is provided, it is difficult to sufficiently reduce the current consumption of the internal power supply circuit. This drawback may be overcome by using a more complicated current regulator circuit; however, in such a case, there will be another drawback that the scale of the current regulator becomes larger.
As described above, in the conventional semiconductor system such as a DRAM memory board, although reduction of data retention current in a stand-by state is desired, it is difficult to reduce the current consumption of the internal power supply circ
Elms Richard
NEC Corporation
Nguyen Van-Thu
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