Semiconductor storage device and resetting method for a...

Static information storage and retrieval – Addressing – Sync/clocking

Reexamination Certificate

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Details

C365S233160, C365S233170

Reexamination Certificate

active

07924651

ABSTRACT:
An exemplary aspect of an embodiment of the present invention is a semiconductor storage device including a power-on reset generator that outputs a first reset signal in accordance with a level of a power supply voltage, a command decoder that moves to a mode set state in accordance with input of an external control pin and outputs mode set information in accordance with a command input from an address pin, an MRS controller that outputs a mode reset signal (MRSPON signal) in accordance with the mode set information, and a reset circuit that outputs a second reset signal initializing each circuit of an operation control section in accordance with the mode reset signal and the first reset signal.

REFERENCES:
patent: 5905690 (1999-05-01), Sakurai et al.
patent: 6826114 (2004-11-01), Lee et al.
patent: 7251171 (2007-07-01), Nishimura et al.
patent: 2006/0203576 (2006-09-01), Nishimura et al.
patent: 01-137494 (1989-05-01), None
patent: 2004-103222 (2004-04-01), None
patent: 2006-252654 (2006-09-01), None

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