Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2000-11-29
2001-12-11
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185300, C365S185330, C365S218000
Reexamination Certificate
active
06330191
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device such as an electrically erasable programmable read only memory (EEPROM) and in particular, to a semiconductor storage device made from an all-at-once erasable flush memory.
2. Description of the Related Art
Currently, various memory devices are uses in various electronic apparatuses. Among such memory devices, there are those which retain a binary data in a rewritable and nonvolatile manner.
The flash memory can be divided into several groups according to an internal structure and a writing method. For example, there are NAND type and NOR type. The NOR type may be AND type or DINOR (divided bit line NOR) type. The DONOR type is considered to be advantageous because of its high speed operation while the AND type is considered to be advantageous for high integration.
Here, explanation will be given on a conventional example of such a semiconductor storage device with reference to
FIG. 4
to FIG.
10
. It should be noted that
FIG. 4
is a plan view schematically showing an entire configuration of a flash memory as the semiconductor storage device;
FIG. 5
is a plan view schematically showing a layered configuration of memory cells;
FIG. 6
is a schematic front view showing a cross section about X—X in
FIG. 5
;
FIG. 7
is a schematic side view showing a cross section about Y—Y in
FIG. 5
;
FIG. 8
schematically shows a state for writing a data in a memory cell;
FIG. 9
schematically shows a state for erasing a data in a memory cell by the substrate erase method; and
FIG. 10
shows a cell threshold value characteristic to memory cells.
Here, a flash memory
100
as a conventional example of the semiconductor storage device includes numerous memory cells
101
which are arranged on the surface of a semiconductor substrate
102
in a two-dimensional structure. As shown in
FIG. 4
, the memory cells
101
are grouped into a plurality of sectors
103
.
Each memory cell
101
consists of at least one MOS transistor having, as shown in
FIG. 5
to
FIG. 7
, a source region
111
, a drain region
112
, a floating gate (FG)
113
, a control gate (CG)
114
, insulation films
115
,
116
and the like. Each of the regions
111
and
112
is a diffused layer formed on the semiconductor substrate
102
. The FG
113
is located on a diffused layer
117
between the regions
111
and
112
.
As has been described above, a plurality of sectors
103
are arranged in the two-dimensional manner on a semiconductor substrate
102
of the flash memory
100
, and on each of the sectors
103
, there are arranged a plurality of memory cells
101
. These memory cells
101
are separated from one another by an element isolation region
118
of LOCOS (local oxidization of silicon) and STI (shallow trench isolation).
It should be noted that in the intermediate region between adjacent sectors
103
, various circuits are arranged including a line decoder, a column decoder, a column selection circuit, a sense amplifier, and the like. For example, the plurality of sectors
103
are arranged in the column direction via a space of “510 (&mgr;m)”, where the column selection circuit (Y selector) is arranged.
Moreover, the plurality of sectors
103
are arranged in the line direction via a space of “330 (&mgr;m)”, where the line decoder (X decoder) is arranged. It should be noted that the space in the line direction of the plurality of sectors
103
where no such circuit is arranged is formed with a width of, for example, “65 (&mgr;m)”.
In the flash memory
100
having the aforementioned configuration, a binary data can be written in each of the memory cells
101
. When writing a new data or rewriting a data stored in the flash memory
100
, the stored data in memory cells
101
are erased on the sector
103
basis immediately before the writing.
When writing a binary data in a memory cell
101
, as shown in
FIG. 8
, a predetermined potential is applied to the source region
111
, the drain region
112
, and the CG
114
and electric charge (electrons) is poured from the semiconductor substrate
102
into the FG
113
.
Here, in the memory cell
101
where a data is to be written, for example, “0 (V)” is applied to the source region
111
, “5 (V)” is applied to the drain region, and “10 (V)” is applied to the CG
114
. Accordingly, an electric charge is poured into the FG
113
and the cell threshold value becomes above a write reference. Simultaneously with this, in a memory cell
101
where no data is to be written, for example, “0 (V)” is applied to the drain region
112
(not depicted) and not electric charge is poured into the FG
113
, thereby the cell threshold value is retained below the erase reference.
As shown in
FIG. 10
, the cell threshold value of the memory cell
101
becomes above the write reference or the below the erase reference. Thus, by detecting this, it is possible to read a binary data which has been written or erased.
When performing such a data read, for example, “0 (V)” is applied to the source region
111
, “1 (V)” is applied to the drain region, and “3 (V)” is applied to the CG
114
, so that the current flowing through the drain region
112
is detected by the sense amplifier (not depicted) to determine the stored data to be 1 or 0.
On the other hand, when erasing data stored in all the memory cells
101
of a certain sector
103
, for example, “−10 (V)” is applied to the CG
114
, “+10 (V)” is applied to the diffused layer
117
, and the source region
111
and the drain region
112
are made into an open state, so that as shown in
FIG. 9
, electric charge (electrons) is discharged from the FG
113
to the diffused layer
117
. As shown in
FIG. 10
, thus, the cell threshold value of the memory cell
101
becomes below the erase reference and in this memory cell
101
, the stored data has been erased.
It should be noted that the aforementioned data erase in the memory cell
101
is performed for each of the sectors
103
. Accordingly, until the cell threshold values of all the memory cells
101
in that sector
103
become below the erase reference, data erase is uniformly performed in all the memory cells
101
of the sector
103
.
However, because of the production errors, the erase speed is not completely identical in all the memory cells
101
. Accordingly, if the data erase is uniformly performed in all the memory cells
101
one sector, the data erase may be performed excessively in a memory cell
101
having a high erase speed.
In that memory cell
101
, the cell threshold value is significantly lowered. However, if a particular memory cell
101
in the flash memory
100
has a too low cell threshold value, there arise a problem of read failure. For example, in an ordinary NOR type cell array, drain regions
112
of a plurality of memory cells
101
are connected to a single bit line. When a predetermined voltage such as “3 (V)” is applied to one of the word lines (CG
114
) of the plurality of the memory cells
101
, the memory cell
101
connected to that word line is selected and the stored data is read out.
Here, if the selected memory cell
101
contains a written data, no detection current is generated and the stored data is determined to be “1” by the sense amplifier, and if the selected memory cell
101
contains no written data, a read current is generated and the stored data is determined to be “0”.
However, in a memory cell
101
where a data erase has been performed excessively, a read current may be generated even when the predetermined voltage is not applied to the word line (CF
114
). That is, even when the memory cell
101
has a written data, the stored data may be determined to be “0”, causing a read failure.
In order to cope with this, in the current flash memory, as shown in
FIG. 10
, when a data erase is performed in a certain sector
103
, electric charge is given to those memory cells
101
having the cell threshold values of the FG
113
below a predetermined lower limit value.
This is called a write-back processing
Ishige Kiyokazu
Nakamura Hitoshi
Saitou Kenji
Sanada Kazuhiko
Lam David
NEC Corporation
Nelms David
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