Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
1999-10-22
2001-08-07
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S185050, C365S185010
Reexamination Certificate
active
06272044
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device. More particularly, the present invention relates to a semiconductor storage device which can continue to operate with no abnormality as a whole even in the failure of some memory transistors in a memory cell, in which information is written and read by applying and receiving electron through tunneling insulating film, such as EEPROM, flash memory, EPROM, FFRAM (memory using ferroelectric).
2. Description of the Related Art
The EEPROM is an example of a semiconductor storage device which can rewrite data electrically and hold it in a non-power supplied state. Such an EEPROM, as shown in
FIG. 4
, is structured so that memory cells, each composed of a pair of a memory transistor MT and a select transistor ST, are arranged in a matrix form in both vertical and horizontal directions. In this semiconductor storage device, the respective sources of the memory cells are coupled to provide a source line ASG (Array Source Ground). The drains of the memory cells arranged vertically are coupled to provide each bit line BL. The gate electrodes of select transistors ST arranged horizontally are coupled to provide each word line WLn. In order that some select transistors of the memory cells coupled vertically can be selected collectively, column lines COLn are provided. The outputs from the column lines are connected to data bus lines, respectively. Incidentally, Vsl serves to apply a reference voltage (sense voltage) Vref to the memory transistors.
The sectional structure of the memory cell is shown in FIG.
5
. As seen from
FIG. 5
, a select transistor ST and a memory transistor MT are formed in a P-type semiconductor substrate. The select transistor is formed to have the following structure. A gate coupled with the word line WL is provided through a gate oxide film
5
, and a N+ drain region
2
and an N+source region
3
are provided on both sides of the gate.
The memory transistor MT is formed to have the following structure. A floating gate
6
is formed through a gate oxide film
5
and a control gate CG is formed through an inter-layer insulating film
7
. A drain region
3
, which also serves as the source region of the above select transistor ST, and a source region
4
are provided on both sides of the control gate CG in a double-stage structure.
The gate oxide film
5
on the drain region
3
of the memory transistor MT has a partial tunnel window
5
a
so as to promote tunneling of electrons. The drain regions
2
of the select transistors ST of the memory cells arranged horizontally on the paper face are coupled to form a bit line BL. The gates of the select transistors of the memory cells arranged vertically to the paper face are coupled to form a word line WL. The source regions of the memory transistors MT are coupled to form an ASG.
The operation of this memory transistor is executed as follows. As seen from
FIG. 6
, in an erasure state H with data of “1”, even when if a voltage Vd is applied between the source and drain, a drain current does not almost flow. On the other hand, in a write state L with data of “0”, the drain current flows. Thus, the write state of the memory transistor can be discriminated from the erasure state.
Referring to
FIG. 7
, an explanation will be given of the relationship among applied voltages in the operation of erasure, write and read.
First, the erasing operation leading to the state of “1” will be carried out as follows. As seen from
FIG. 7A
, a pulse voltage waveform V
CG
of Vpp at a high potential is applied to the control gate of a memory transistor MT through a byte select transistor BST. A bit line BL and a source ASG are connected to earth GND. Thus, electrons are injected into the floating gate through a tunnel window
5
a
so that the memory transistor is placed into an erasure state.
The write operation leading to the state of “0” will be carried out as follows. As seen from
FIG. 7B
, the pulse voltage waveform V
CG
of Vpp at the high potential is applied to the bit line BL. The source line ASG is placed in an open state and the control gate CG of the memory transistor is connected to earth GND. Thus, electrons stored in the floating gate are drawn out so that the memory transistor is placed in the write state.
In order to write “1” (erase) in another column while “0” is written in the pertinent column, as seen from
FIG. 7C
, with the source line ASG and control gate CG placed in the same state as the state with “0” written, the bit line BL is connected to earth GND.
The read operation will be executed as follows. As seen from
FIG. 7D
, a reference voltage Vref is applied to the control gate CG and a prescribed potential is applied to the bit line BL. In this case, if the stored data is “1” (erasure state), as described above, the current does not almost flow. Therefore, the prescribed potential is outputted as it is and detected as data of “1”. If the data is “0” (write state), as. described above, the current flows so that the voltage lowers to provide a low potential as seen from FIG.
7
D. In this way, the erasure state and write state can be discriminated from each other.
Such a semiconductor storage device is composed of a large number of the above memory cells arranged in a matrix form. For example, EEPROM is composed of several thousands to several hundred thousands of memory cells. If any one of these memory cells suffers a failure, the entire semiconductor device does not operate normally. In order to repair such a partial failure at an initial stage of manufacturing the semiconductor storage device, a technique has been proposed which replaces a faulty memory cell by a normal memory cell for repair. Such a failure seldom occurs. However, if failure of a single memory cell occurs while the semiconductor storage device installed in a system operates normally, it cannot be repaired. Particularly, as described above, a semiconductor storage device is likely to produce dielectric breakdown in a tunnel window portion as described above. While it operates for a long time, it may produce dielectric breakdown. This attenuates the reliability of the semiconductor storage device.
For example, in the conventional EEPROM, a silicon oxide film having a thickness of 90 A or less was used as the gate insulating film. Therefore, while the EEPROM is used repetitively, it deteriorates during tunneling, leading to dielectric breakdown.
The present invention has been accomplished in order to solve the problems described above.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a reliable semiconductor storage device which can operate normally even when some transistors in memory cells suffer a failure. A second object of the present invention is to provide a method of driving such an improved semiconductor storage device.
In order to attain the first object, in accordance with the present invention, there is provided a semiconductor storage device comprising a plurality of memory cells formed in a matrix form in a semiconductor substrate, write and read for each of which is carried out through a word line and bit line, wherein each of the memory cells includes two memory transistors connected in series.
In this configuration, even if any one memory transistor produces any inconvenience such as dielectric breakdown, the memory transistor is short-circuited and the other memory transistor of the two memory transistors operates normally. This greatly improves the reliability of the semiconductor storage device.
Here, the series connection implies that the source of the one memory transistor is connected to the drain of the other transistor.
A first aspect of the device is a semiconductor storage device comprising a plurality of memory cells each having a select transistor and a memory transistor means, for each of which write and read for each of which is carried out in such a manner that a voltage is applied to a word line and bit line of the memory transistor means so that write
Tada Yoshihiro
Yamamoto Hiroki
Hoang Huan
Morgan & Lewis & Bockius, LLP
Rohm & Co., Ltd.
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