Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-07-10
2003-03-04
Lam, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S233100, C365S233500
Reexamination Certificate
active
06529408
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims priority to Japanese Patent Application Number 2000-209122 filed Jul. 10, 2000, the content of which is incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device and a method for evaluating the same. Specifically, the present invention relates to a semiconductor storage device where a deviation of an internal timing for reading data, which results from a variation of characteristics of elements constituting the semiconductor storage device during a fabrication process thereof, can be eliminated after the fabrication process is completed so that an optimum internal timing is obtained, and to a method for evaluating such a semiconductor storage device. Furthermore, the present invention relates to a semiconductor storage device whose specification can be changed after the fabrication thereof is completed so as to provide various types of products (e.g., a product having an 8-bit input/output terminal or a product having a 16-bit input/output terminal), and to a method for evaluating such a semiconductor storage device. Especially, the present invention relates to a semiconductor storage device which is preferably used in the case where semiconductor storage devices based on different supply voltage specifications (e.g., 5 V and 3.3 V) are produced from a same chip design, and to a method for evaluating such a semiconductor storage device.
2. Description of the Related Art
In the semiconductor storage device industry, for the purpose of satisfying various needs of customers, manufacturers supply a line of semiconductor storage devices which have the same storage capacity but different specifications, e.g., the supply voltage for operation (operation supply voltage), the operation speed, the bit width at which data can be input/output at one time, etc. However, even if various types of semiconductor storage devices are produced based on different specifications, these semiconductor storage devices generally have a common circuit configuration, because it is inefficient to design a circuit of a semiconductor storage device in order to realize an optimum configuration for each product type. In order to provide adjustment to various specifications without deteriorating the production efficiency, semiconductor storage devices having a common circuit configuration are fabricated, and means for changing specifications in accordance with necessity is provided to the semiconductor storage devices.
Conventionally, specifications are altered by changing the bonding arrangement or by disconnecting a trimming fuse. Furthermore, using such known methods, a deviation of a specification value from a desired designed value (desired specification value), which results from variation of characteristics caused during a fabrication process, is corrected in a conventional technique.
Change in specifications as to a function of a semiconductor storage device, e.g., the bit width at which data can be input/output at one time, etc., is performed using a logical method which is achieved by switching control circuits related to the function. However, change in specifications regarding performance of a semiconductor storage device, e.g., the operation supply voltage, the operation speed, etc., and correction of a deviation from a desired specification value, require timing adjustments of a synchronization signal for an internal operation of the semiconductor storage device.
A typical synchronization signal used in semiconductor storage devices is an address transition detector (ATD) pulse signal. This signal is a pulse signal generated in response to an externally-supplied address signal, or the like, and used for synchronization of an internal operation. In synchronization with this ATD pulse signal, circuits insides a semiconductor storage device are operated, whereby a high speed operation is achieved. The ATD pulse signal is generated by a synchronization signal generation circuit (hereinafter, “ATD pulse generation circuit”) in response to an externally-supplied address signal, or the like.
For example, in the case where a semiconductor storage device arranged for use with a 3.3 V supply voltage and a semiconductor storage device arranged for use with a 5 V supply voltage are produced based on a same chip design, if the ATD pulse signal is optimized for a 3.3 V supply voltage specification, the operation speed of the semiconductor storage device is decreased when operated at the supply voltage of 5 V. On the other hand, if the ATD pulse signal is optimized for a 5 V supply voltage specification, the semiconductor storage device does not operate at the supply voltage of 3.3 V. This is because the pulse width of the ATD pulse signal optimized for a 3.3 V supply voltage specification differs from the pulse width of the ATD pulse signal optimized for a 5 V supply voltage specification.
In order to address such problems, in general, the bonding arrangement is changed or the trimming fuse is disconnected, whereby the pulse width of the ATD pulse signal is adjusted such that the semiconductor storage device operates at the supply voltage of 3.3 V.
FIGS. 12 and 13
each show an example of an address input buffer ABUF and an ATD pulse generation circuit ATDPG inside a Static Random Access Memory (SRAM), which is a volatile semiconductor memory, in a conventional semiconductor storage device.
In the semiconductor storage device shown in
FIG. 12
, the pulse width of the ATD pulse signal is adjusted by utilizing a trimming fuse. Specifically, the potential of an inverter INV
13
which connects to an internal timing adjustment signal ITC and a logical threshold adjustment signal VLTC is changed based on whether or not the trimming fuse is disconnected by a laser beam, whereby the pulse width of the ATD pulse signal is adjusted. When the supply voltage is 5 V, in order to make the logical threshold adjustment signal VLTC and the internal timing adjustment signal ITC be at a high level, the trimming fuse is not disconnected so that the potential input to the inverter INV
12
is equal to the supply potential Vcc. When the supply voltage is 3.3 V, in order to make the logical threshold adjustment signal VLTC and the internal timing adjustment signal ITC be at a low level, the trimming fuse is disconnected by a laser beam so that the potential input to the inverter INV
12
is equal to the ground potential GND.
In the semiconductor storage device shown in
FIG. 13
, the pulse width of the ATD pulse signal is adjusted by changing the bonding arrangement. Specifically, the internal timing adjustment signal ITC and the logical threshold adjustment signal VLTC which control an internal timing of the semiconductor storage device are connected to a bonding pad BPAD. The potential of the bonding pad BPAD is determined by whether the bonding pad BPAD is connected to a power line of a lead frame (i.e., the supply potential Vcc) or a ground line of the lead frame (i.e., ground potential GND), whereby the pulse width of the ATD pulse signal is adjusted. When the supply voltage is 5 V, in order to make the logical threshold adjustment signal VLTC and the internal timing adjustment signal ITC be at a high level, the bonding pad BPAD is connected to the power line Vcc. When the supply voltage is 3.3 V, in order to make the logical threshold adjustment signal VLTC and the internal timing adjustment signal ITC be at a low level, the bonding pad BPAD is connected to the ground line GND. An example of such a method for adjusting the pulse width of the ATD pulse signal by changing the bonding arrangement is disclosed in Japanese Laid-Open Publication No. 11-176166.
Next, steps for such an adjustment and change of a specification which are achieved by utilizing a trimming fuse are specifically described below.
In general, a semiconductor storage device includes: electric circuits on a semiconductor substrate, such as transistors, resistors, capacitors, and the like; i
Lam David
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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