Semiconductor storage device

Static information storage and retrieval – Interconnection arrangements – Transistors or diodes

Reexamination Certificate

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Details

C257S204000, C257S205000, C257S206000

Reexamination Certificate

active

11143580

ABSTRACT:
A semiconductor storage device in which a pair of wiring lines extending in a first direction are arranged repeatedly with a predetermined pitch, comprising: a group of pair transistors in which a plurality of pair transistors is arranged according to a repetition unit with a predetermined pattern, the pair transistors composed of a MOS transistor of which a gate is connected to one line of the pair of wiring lines and of another MOS transistor of which a gate is connected to the other line of the pair of wiring lines, wherein the repetition unit of the group of pair transistors includes a plurality of the pair transistors such that two MOS transistors are adjacent to each other in the first direction, and at least one pair of pair transistors such that two MOS transistors are not adjacent to each other and diagonally opposite to each other.

REFERENCES:
patent: 5834851 (1998-11-01), Ikeda et al.
patent: 6700169 (2004-03-01), Kuroki
patent: 6747320 (2004-06-01), Nakabayashi
patent: 2001/0019503 (2001-09-01), Ooishi
patent: 2001/0026496 (2001-10-01), Hidaka
patent: 2003/0173593 (2003-09-01), Miyatake et al.
patent: 2004/0124440 (2004-07-01), Takemura et al.
patent: 11-307741 (1999-11-01), None
patent: 2000-22108 (2000-01-01), None

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