Semiconductor storage device

Static information storage and retrieval – Floating gate

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3651851, G11C 1300

Patent

active

060882611

ABSTRACT:
In a write operation, input data sequences "00", "01", "10", and "11" are converted into identification number groups "00", "02", "20", and "22", respectively, and the individual figures are stored in a pair of three-level memory cells. If a data error occurs during a read operation, the probable transition is only a transition from an upper state in which electric charge is stored in a memory cell to a lower state in which electric charge is reduced, i.e., only a first transition of only one of the identification numbers from state "2" to state "1" or from state "1" to state "0". Error correction is performed by taking account of this property, and a correct data sequence is output. This allows very efficient and accurate error correction when multi-level data using three or more values is written or read out.

REFERENCES:
patent: 4527257 (1985-07-01), Cricchi

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