Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2006-05-16
2006-05-16
Tran, M. (Department: 2827)
Static information storage and retrieval
Addressing
Sync/clocking
C365S222000
Reexamination Certificate
active
07046579
ABSTRACT:
The semiconductor storage device has a clock input buffer to output an internal clock signal INCLK, a NOT circuit to receive an external signal /CS, and an OR circuit to receive the output of the NOT circuit and a refresh request signal RFR and output their logical sum as an internal clock enable signal INCE to the clock input buffer. The clock input buffer has a NAND circuit to receive a clock signal CLK and the internal clock enable signal INCE and output an inverted signal of their logical product.
REFERENCES:
patent: 4412314 (1983-10-01), Proebsting
patent: 5262998 (1993-11-01), Mnich et al.
patent: 6026029 (2000-02-01), Dosaka et al.
patent: 2002-184180 (2002-06-01), None
patent: 2003-85970 (2003-03-01), None
Data Sheet Elpida, 128M bits Mobile RAM, Document No. E0195E50 (Ver.5.0) p. 43.
Tran M.
Young & Thompson
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