Semiconductor storage device

Details Semiconductor storage device Semiconductor storage device

2002-10-21

2004-10-26

Lam, David (Department: 2818)

Static information storage and retrieval

Addressing

Including particular address buffer or latch circuit...

C365S233500, C365S233100

Reexamination Certificate

active

06809989

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor memory device which latches an address applied from the outside and uses it in internal chip operations, and more particularly relates to the semiconductor memory device which detects changes in the address applied from the outside as a trigger for latching the address, and uses it in internal operations.
BACKGROUND ART
There is a conventional semiconductor memory device which, after latching an address applied from the outside, uses the latched address in operations of circuits positioned at later stages.
FIG. 10
is a circuit diagram showing a schematic constitution of the path to latching the address applied from the outside in a semiconductor memory device of this type.
A number of address buffers
100
are provided in accordance with the number of bits in an input address IN, supplied from outside the semiconductor memory device, and the number of latches in a latch circuit
101
is the same as the number of address buffers
100
. The output from the latch circuit
101
is used in operations of many circuit parts positioned at later stages. Furthermore, the input address IN is input to the latch circuit
101
after being buffered by the address buffer
100
.
While an address latch signal AL is at the low level (hereinafter abbreviated as “L”), the latch circuit
101
passes addresses sent from the address buffer
100
. Then, when the value of the input address IN has been determined, an unillustrated timing signal generating circuit generates a pulse as the address latch signal AL. Using the rise of this pulse as a trigger, the latch circuit
101
latches the address output from the address buffer
100
and outputs to unillustrated circuits positioned at later stages than the latch circuit
101
. Furthermore, these circuits also use the pulse of the address latch signal AL as a trigger, and commence operations based on the output of the latch circuit
101
.
In this way, the conventional semiconductor memory device is configured so that the output of the address buffer
100
is input unaltered to the latch circuit
101
. For this reason, when the address latch signal AL rises while noise which has been generated inside and outside the chip superimposes on the input address IN, there is a danger that the latch circuit
101
will latch the address containing noise, so that the value of the address will be in error depending on the size of the noise.
In particular, when noise superimposes on the address immediately before the latch circuit
101
latches the address, the latching operation is performed while the effects of the noise remain, increasing the danger of a mistaken address being latched. Since circuits positioned at later stages than the latch circuit
101
commence operations in accordance with the generation of the address latch signal AL, they will use the mistaken address output from the latch circuit
101
and perform malfunctions.
In addition to the above, an information processing apparatus is disclosed in, for instance, Japanese Unexamined Patent Application, First Publication No. Hei 8-203273, as a method of removing noise such as glitches from a memory address. In this information processing apparatus, a noise-canceling circuit is provided between a memory controller and the semiconductor memory device (memory). Then, the noise-canceling circuit operates based on a strobe signal for predicting changes in the memory address, and removes noise on the memory address supplied from the memory controller to the memory. However, this information processing apparatus can do nothing more than remove noise on the memory address supplied to the memory from the memory controller, and provides no countermeasures whatsoever against noise generated inside the memory. Consequently, there is a problem of malfunctions when, for example, power source noise and the like has been generated inside the memory and superimposed on the memory address.
Furthermore, even in the case where the noise-canceling circuit and the memory are integrated to form a single chip, and the noise-canceling circuit attempts to remove noise generated within the memory, there is no countermeasure against noise which is fed back from circuit inside the chip to the noise-canceling circuit at the entrance of the chip. Therefore, there is a possibility of malfunctions due, for example, to noise on the strobe signal itself, which is supplied to the noise-canceling circuit.
Moreover, in a constitution using the strobe signal, since the operations performed within the system are substantially similar to those when using a clock in a synchronous semiconductor memory device, power consumption in the system increases. For this reason the above information processing apparatus has a problem that it cannot be applied in mobile products where low power consumption is a requirement, such as in a mobile telephone, which is one of the products which the present invention is to be applied in. The information processing apparatus mentioned above has various other problems, such as having a more complex system due to the need for a timing mechanism between the strobe signal and the memory address, the problem that the strobe signal itself becomes a source of noise, and so on.
DISCLOSURE OF THE INVENTION
The present invention has been realized in consideration of the points described above, and aims to provide a semiconductor memory device which does not malfunction after capturing a mistaken address appearing noise, whether the noise has been generated inside or outside the chip. Other objects of the present invention will become clear from the embodiments of the invention described below.
In order to achieve the above object, a semiconductor memory device according to a first aspect of the present invention comprising a control circuit that comprises: a latch circuit for latching a second address signal for a predetermined period and outputting a first address signal to a predetermined circuit; and a filter circuit for outputting a signal whose sensitivity with respect to an input address signal having been lowered, to the latch circuit as the second address signal during a period including the time when the latch circuit latches the second address signal, the predetermined circuit including memory cells operating in response to the first address signal. Consequently, there is no danger that the latch circuit latches an incorrect input address signal, leading to a malfunction, even if noise generated inside or outside a chip superimposes on an address.
In the semiconductor memory device according to the first aspect, the filter circuit may lower the sensitivity with respect to the input address signal from a predetermined time after the input address signal has been determined until at least the time when the latch circuit latches the second address signal. Consequently, this increases the resistance to system noise and the like from the outside immediately before latching, which is the time when there is the greatest danger of an incorrect address appearing noise being latched. Furthermore, while the input address signal is changing due to the skew, the change can be transmitted speedily to circuits positioned at later stages than the latch circuit. Moreover, when the input address signal has been determined, changes therein need not be speedily transmitted, and therefore, effects of noise generated inside and outside the chip can be cancelled by lower the sensitivity to the input address signal.
In the semiconductor memory device according to the first aspect, when the timing of starting to lower the sensitivity with respect to the input address signal has coincided with the timing of noise superimposing on the second address signal supplied to the latch circuit, the filter circuit starts to lower the sensitivity with respect to the input address signal, using the timing of the latching of the second address signal by the latch circuit as a reference, at least before the time required to return to a level where the input address signal on which noise

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