Static information storage and retrieval – Floating gate – Particular connection
Reexamination Certificate
2001-06-12
2003-02-18
Nelms, David (Department: 2818)
Static information storage and retrieval
Floating gate
Particular connection
C365S181000, C365S185040, C365S226000
Reexamination Certificate
active
06522581
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device.
2. Description of the Related Art
A non-volatile memory is characterized in that data stored in that memory is not deleted even after the power thereto is turned off. In this point, the nonvolatile memory is different from a volatile memory such as a Dynamic Random Access Memory (DRAM), a Static Random Access Memory (SRAM), or the like, from which data is deleted when the power thereto is turned off. Examples of the non-volatile memory include a flash memory (EEPROM) which is used for various applications such as portable phones, etc., a ferroelectric memory (FRAM) which is used in an IC card, etc., a magnetic memory (MRAM) which has been actively developed, and the like.
FIG. 1
schematically shows a structure of a flash memory cell for used in a non-volatile semiconductor storage device. A flash memory cell
10
shown in
FIG. 1
has a control gate
2
, a floating gate
3
, a source
4
, and a drain
5
. Data, “1” or “0”, is stored in this flash memory cell
10
according to the quantity of electrons infected in the floating gate
3
. A plurality of such flash memory cells
10
are arranged into a plurality of matrix blocks each formed by mxn cells
10
, and the matrix blocks are connected to one another, whereby a flash memory array (nonvolatile semiconductor storage device) is formed.
FIG. 2
shows a structure of an NOR-type flash memory, and especially, shows a relationship between an X-decoder and word lines. As shown in
FIG. 2
, the NOR-type flash memory includes a pair of matrix blocks BLK
1
and BLK
2
formed by a plurality of flash memory cells
10
. In each matrix block, control gates
2
of n flash memory cells
10
in a row are connected to a corresponding one of m word lines WL
1
to WLm, and drains
5
of m flash memory cells
10
in a column are connected to a corresponding one of n bit lines BL
1
to BLn. In the blocks BLK
1
and BLK
2
, all of the sources
4
of the flash memory cells
10
are connected to a single common source line S.
As shown in
FIG. 2
, in each block of the flash Memory array, sources
4
of the flash memory cells
10
are commonly connected to the single source line S. In such a structure, data stared in the flash memory calls
10
in one block is deleted all together and cannot be deleted from each of the flash memory cells
10
, i.e., cannot be deleted on a bit-by-bit basis.
Reading, writing, and deleting of date In the flash memory array shown in
FIG. 2
is now briefly described. When data stored in some of the flash memory cells
10
is read out, read signals including a control signal, an address signal, etc., are supplied from a central processing unit (CPU: not shown), or the like, externally connected to the flash memory array so that a high voltage of, for example, 5 V is applied to a control gate
2
of the flash memory cell
10
, a low voltage of, for example, 1 V is applied to a drain
5
of the flash memory cell
10
, and a low voltage of, for example, 0 V is applied to a source
4
of the flash memory cell
10
. At this time, the magnitude of a current which flows between the source
4
and the drain
5
is sensed by a sense amplifier (not shown), thereby determining whether data is “1” or “0”. Then, the data read from the flash memory cell
10
is output outside of the flash memory, whereby a data reading operation is completed.
Writing of data in the flash memory array is performed as follows. When a control signal, an address signal, and data are supplied from a CPU or the like, which is externally connected to the flash memory array, are supplied to the flash memory array, in some of the flash memory cells
10
which is designated by the address signal, a high voltage of, for example, 12 V is applied to the control gate
2
, a high voltage of, for example, 7 V is applied to the drain
5
, and a low voltage of, for example, 0 V is applied to the source
4
. By applying such voltages, hot electrons are generated in the vicinity of the junction of the drain
5
, and the generated hot electrons are injected into the floating gate
3
due to the high voltage applied to the control gate
2
. Thereafter, such a writable state is ended, and a verification operation is performed. After the writing of data in the flash memory cell
10
has been completed, if the verification operation is successful, the writing operation is completed. If the verification operation is unsuccessful, writing of the data, and the verification operation, are performed again. If the verification operation is unsuccessful again, writing of the data, and the verification operation, are further performed a predetermined number of times. If the verification operation is still unsuccessful, the CPU or the like recognizes it as a write error.
Lastly, an erasing operation of the flash memory array is described. Data in the flash memory array is erased on a block by block basis. A control signal, a block address, and a deletion command are supplied from the CPU or the like to the flash memory array so that a low voltage of, for example, −10 V is applied to the control gate
2
, the drain
5
is floated, and a high voltage of, for example, 6 V is applied to the source
4
. With application of such voltages, a high electric field is generated between the floating gate
3
and the source
4
, and electrons in the control gate
2
can be taken out therefrom by means of tunneling, whereby the data is deleted.
Thereafter, such a data erasable state is ended, and a verification operation is performed similarly to that for the writing of data. If the verification operation is successful for all of the flash memory cells
10
in the block to which the deletion command is supplied, the data deletion operation is completed. If the verification is unsuccessful, deletion of the data, and the verification operation, are performed again. If the verification operation is still unsuccessful after deletion of the data, and the verification operation, has been performed a predetermined number of times, the CPU or the like recognizes it as an erase error.
In a typical flash memory array, an erase operation including a verification operation requires a longer time than a program operation including a verification operation, and a program operation including a verification operation requires a longer time than a read operation. Specifically, the read operation requires about 100 ns, the program operation including the verification operation requires about 30 &mgr;s, and the erase operation including the verification operation requires about 500 mm. Thus, in the flash memory array, a considerably longer time is required for writing and erasing of data as compared with reading of data. It should be noted that, in this specification, a “program operation” in a non-volatile memory (e.g., flash memory) means writing of data in the non-volatile memory.
On the other hand, a volatile semiconductor storage device, such as a DRAM, an SRAM, etc., loses data stored therein when the power to the storage device is turned off. However, the time required for writing data in the storage device is substantially the same as that required for reading the data therefrom. For example, in an SRAM, only about 100 ns is required for completing each of a write operation and a read operation. Thus, in the SRAM, replacing of data can be completed in a considerably shorter time as compared with the time required for erasing and writing of data in the flash memory array.
FIG. 3
shows a typical memory cell of a SRAM. An SRAM memory cell
6
shown in
FIG. 3
is formed by a pair of switch transistors
7
and a pair of inverters
8
. Reading of data from the SRAM memory cell
6
is now described. In a read operation in the SRAM memory cell
6
, in the first step, a pulse voltage is applied to a word line WL which is selected by an address signal, whereby any of the switch transistors
7
is turned on. At this time, a voltage at a BIT terminal and a voltage at a BIT# terminal are com
Fukui Haruyasu
Sumitani Ken
Takata Hidekazu
Morrison & Foerster / LLP
Nguyen Dao H.
Sharp Kabushiki Kaisha
LandOfFree
Semiconductor storage device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor storage device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor storage device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3143677