Static information storage and retrieval – Addressing – Sync/clocking
Reexamination Certificate
2000-11-16
2002-03-12
Nelms, David (Department: 2818)
Static information storage and retrieval
Addressing
Sync/clocking
C365S189050, C365S189080, C365S230080
Reexamination Certificate
active
06356508
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor storage device, and specifically to a semiconductor storage device having an input data hold circuit which operates in synchronization with a rising edge of a system clock signal.
2. Description of the Related Art
In recent years, along with the increase in operation speed of microprocessors, etc., demand for semiconductor storage devices which operate at higher speed has been growing. A semiconductor storage device developed for the purpose of meeting such a demand is a synchronous semiconductor storage device that operates in a synchronous burst operation mode. In such a storage device, high speed readout of data is achieved in addition to the increase in speed for normal random access, although an access method is limited to some extent.
The synchronous burst operation mode used in a clock synchronous semiconductor storage device is a high speed access mode in which predetermined data rows are sequentially output in synchronization with a system clock signal.
One example of a synchronous semiconductor storage device which operates in a synchronous burst operation mode includes a synchronous DRAM (hereinafter, referred to as “SDRAM”). In an SDRAM, upon receiving the system clock signal, an input circuit receives, in synchronization with a rising edge of the pulse of the system clock signal, control signals (a row address strobe signal, a column address strobe signal, a write enable signal, and a chip select signal) and an address signal from outside in a time-division manner.
When the control signals and the address signal are received in synchronization with a rising edge of a system clock signal, it is necessary that the control signals and the address signal are input with consideration for a certain setup time and a certain hold time with respect to the rising edge of the system clock signal. In high speed devices such as SDRAMs developed in the recent years, as the frequency of the system clock signal increases, the setup time and the hold time are reduced. Thus, in the margin settings of the setup time and the hold time based on the specification of a storage device, a reduction in dead time is demanded more than ever.
For the purpose of meeting such a demand, a structure of a flip-flop for latching a data signal, which compensates for the setup time, has been proposed. In general, it is necessary to delay an internal clock signal when an input data signal and a system clock signal are input so that waveforms of these two signals rise up at almost the same timing. However, such a delay of the internal clock signal delays the output of data. In the proposed structure, the difference between a delay of the control signals and the address signal in an input data latch circuit section and a delay of a rising edge of the system clock signal is eliminated, whereby the setup time is compensated.
FIG. 8
shows a latch circuit
800
disclosed in Japanese Laid-Open Publication No. 2-203611. In the latch circuit
800
, a chip select signal CS, and an address signal (A
0
-Ax) are input to a logic circuit
204
through a CS input buffer
202
and an address buffer
203
, respectively. The logic circuit
204
outputs a signal &phgr;
204
to a latch circuit
20
. The latch circuit
20
includes a transfer gate
21
a
, a transfer gate
22
a
, an inverter INV
21
, an inverter INV
22
, an inverter INV
23
, an inverter INV
24
, and an inverter INV
25
. The transfer gate
21
a
includes an NMOS transistor N
21
and a PMOS transistor P
21
. The transfer gate
22
a
includes an NMOS transistor N
22
and a PMOS transistor P
22
.
Upon receiving a clock signal CLK, a CLK input buffer
205
outputs a CLK input buffer output signal &phgr;
205
. A delay circuit
201
receives the CLK input buffer output signal &phgr;
205
and outputs a signal &phgr;
201
to the transfer gate
21
a
and the transfer gate
22
a
. Specifically, the signal &phgr;
201
is input directly to a gate of the PMOS transistor P
21
and a gate of the NMOS transistor N
22
, and input through the inverter INV
25
to a gate of the NMOS transistor N
21
and a gate of the PMOS transistor P
22
.
The signal &phgr;
204
from the logic circuit
204
is supplied to the transfer gate
21
a
of the latch circuit
20
. A signal output from the transfer gate
21
a
is supplied to the inverter INV
21
. A signal output from the inverter INV
21
is supplied to the transfer gate
22
a
and is also fed back to the inverter INV
21
through the inverter INV
22
. An output of the transfer gate
22
a
is output from the latch circuit
20
through a feedback loop formed by the inverter INV
23
and the inverter INV
24
, and supplied to a transfer gate
23
a.
The signal output from the delay circuit
201
is also supplied through an inverter INV
26
to one of input terminals of a NAND gate NAND
21
. The other input terminal of the NAND gate NAND
21
receives the CLK input buffer output signal &phgr;
205
from the CLK input buffer
205
. An output of the NAND gate NAND
21
is supplied to gates of the transfer gate
23
a
and gates of a transfer gate
24
a
. The transfer gate
23
a
includes an NMOS transistor N
23
and a PMOS transistor P
23
. The transfer gate
24
a
includes an NMOS transistor N
24
and a PMOS transistor P
24
. The output of the NAND gate NAND
21
is supplied directly to a gate of the NMOS transistor N
23
and a gate of the PMOS transistor P
24
, and is also supplied through the inverter INV
27
to a gate of the PMOS transistor P
23
and a gate of the NMOS transistor N
24
. The signal &phgr;
204
from the logic circuit
204
is also supplied to the transfer gate
24
a
. A buffer Buf
21
receives an output of the transfer gate
23
a
and an output of the transfer gate
24
a
, and outputs a signal &phgr;
21
.
In the latch circuit
800
having the above structure, an internal clock signal is delayed so as to obtain a margin for a setup time, whereby the delay of the input data signal (A
0
-Ax) with respect to the internal clock signal is eliminated.
Specifically, in the latch circuit
20
whose setup time determined based on the specification of the latch circuit
20
is 0, the input data signal (A
0
-Ax) and the system clock signal CLK arrive at the latch circuit
20
at the same time. Utilizing this, the system clock signal is delayed by the delay circuit
201
to generate an internal clock signal. Until the input data signal (A
0
-Ax) is latched based on the internal clock signal, the already-arrived input data signal (A
0
-Ax) is routed through a path different from the latch circuit
20
, i.e., through the transfer gate
23
a
and the transfer gate
24
a
(which have been turned on), and are output from the buffer Buf
21
.
According to this system, the address data signals are input under the timing control of data input control command signals (RAS, CAS, WE, and CS). Therefore, it is required to hold the address data signal when the data input control command signals are input, in order to obtain an input data signal for internal access. For the purpose of solving such a problem, an input data hold circuit
900
(
FIG. 9
) further including a latch circuit
51
for holding signals has been proposed.
In the input data hold circuit
900
, a signal &phgr;
52
generated by a latch circuit
53
having the same structure as that of the latch circuit
800
as shown in
FIG. 8
is supplied to a latch circuit
51
. The latch circuit
51
includes a transfer gate
55
a
, a transfer gate
56
a
, an inverter INV
59
, an inverter INV
510
, an inverter INV
511
, an inverter INV
512
, an inverter INV
513
. The transfer gate
55
a
includes an NMOS transistor N
55
and a PMOS transistor P
55
. The transfer gate
56
a
includes an NMOS transistor N
56
and a PMOS transistor P
56
.
The signal &phgr;
52
generated by the latch circuit
53
is supplied to the transfer gate
55
a
. An input data control signal &phgr;
120
is supplied to a gate of the PMOS transistor P
55
and a gate of the NMOS transistor N
56
. Furthermore, the input data control
Auduong Gene N.
Morrison & Foerster / LLP
Sharp Kabushiki Kaisha
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