Static information storage and retrieval – Addressing – Plural blocks or banks
Reexamination Certificate
2001-03-20
2002-05-21
Phan, Trong (Department: 2818)
Static information storage and retrieval
Addressing
Plural blocks or banks
C365S230060, C365S207000
Reexamination Certificate
active
06392951
ABSTRACT:
TECHNICAL FIELD
The present invention relates generally to semiconductor storage devices, and more particularly to sensing circuitry commonly used between a plurality of banks in a semiconductor storage device.
BACKGROUND OF THE INVENTION
Semiconductor storage devices, such as a Dynamic Random Access Memory (DRAM) store data on storage capacitors in a storage cell. Data can be read from or written to a storage cell by charging or discharging a storage capacitor. Because the charge on a storage capacitor is very small, it is required to sense the charge using a sense amp when data is read from a particular storage cell. Such charging/discharging can prevent the semiconductor storage device from operating at speeds as high as the central processing unit (CPU) requesting the information from the semiconductor storage device.
In order to improve operating speeds, semiconductor storage devices have been developed that divide a memory array into a plurality of independently operated banks of memory cells. The banks are then operated simultaneously in a manner such that one bank can be transmitting or receiving data while another is being activated and having a row of data sensed in preparation for an access operation to or from the bank. Such a semiconductor storage device can be considered to be composed of separate memory chips because each of the banks can operate independently.
An example of a semiconductor storage device using a multi-bank structure is disclosed in Japanese Patent Application Laid-Open No. Hei 9-219091. The semiconductor storage device disclosed in Japanese Patent Application Laid-Open No. Hei 9-219091 is a synchronous DRAM (SDRAM) which operates in synchronization with an edge of an externally supplied clock. The SDRAM disclosed in Hei 9-219091 is composed of a small number of banks, such as four.
Because each of the banks can be independently operated, in order to simultaneously activate a plurality of banks, control circuits are provided separately for each bank. For each bank, separate signal lines for transmitting various signals from the control circuits to the banks must also be provided. Control circuits include a row decoder (X-address decoder) and a column decoder (Y-address decoder) that decode external address signals. Control circuits can also include buffers that receive external control and address signals, and a row of sense amplifiers for sensing the logic level stored in a row of memory cells. Control circuits can also include control circuits for generating timing signals that control the previously mentioned circuits under various modes of operation.
Even when control circuits and control signal lines are provided for each of the banks, significant adverse problems can be minimized as long as the number of banks remain as low as four. However, when the number of independently operating banks increases beyond four to, for example, sixteen, thirty-two, etc., an adverse problem of an increased chip size corresponding to the increased number of banks can be problematic. Particularly, the chip area occupied by timing control circuits can be significantly large as compared to the chip area occupied by other circuits. Thus, as higher speed operation is needed such that the number of independently operating banks increases, chip size can be adversely affected.
In the above example, commands are externally supplied to the semiconductor storage device. A command decoder can receive these commands. Timing control circuits can receive the decoded commands and generate respective timing control signals by appropriately delaying signals to give desired timings. The delay can be provided by a plurality of inverters connected in series. These chains of inverters can result in an increased chip area occupied by the timing control circuits. Because some of the timing control signals are to be supplied to other areas of the semiconductor storage device or to a large number of circuits within a bank, the final driver stage needs a large current driving capability. This can require the final driver stage to include large sized transistors, which can further increase chip size.
In view of the above, a portion of control circuits provided for each of the banks is often shared. One such scheme includes a semiconductor storage device in which sense amplifier circuits are shared by adjacent banks. Such a configuration will now be described with reference to a number of drawings.
Referring now to
FIG. 10
, a block schematic diagram of a semiconductor storage device, having sense amplifiers shared by adjacent banks, is set forth and designated by the general reference character
1000
. Semiconductor storage device
1000
illustrates components associated with bank activation up to sensing data from a row of memory cells in a bank. Other components that are included in a DRAM, in general, and known to those skilled in the art, have been omitted. Such circuits include, respective memory cells, precharging circuits, column (Y-address) decoders, column selection switches, input/output (I/O) lines, read/write amplifiers, output buffers, I/O pads, etc have been omitted from the illustration for clarity.
Semiconductor storage device
1000
includes sixteen banks (B
0
to B
15
). Each bank (B
0
to B
15
) has an identical configuration. Each bank (B
0
to B
15
) includes a plurality of word lines (not shown) arranged along the row direction and a plurality of bit line pairs (partially shown) arranged in a column direction. Memory cells (not shown) are provided at cross-points of the word lines and the bit lines.
When a row address activation signal RAA becomes active (high in this case), a timing control circuit
1
activates an address enable signal AE and a sense enable signal SE (both high) at predetermined timings. These timings will be explained more in detail in accordance with the description of the present invention.
Row address buffer
2
receives an external address signal ADR and generates a row address signal RA when address enable signal AE becomes active (high).
Bank decoder
3
activates one of bank selection signal (BS
0
to BS
15
) according to the value of a bank address included in address signal ADR.
Bank enable signal generation circuits (EC
0
to EC
15
) are provided to correspond to banks (B
0
to B
15
) respectively. A particular bank enable signal generation circuit ECn (where n can be an integer from 1 to 14) sets a bank enable signal BEn of the corresponding bank Bn to an enable state (high in this case) only when a bank selection signal BSn of the corresponding bank Bn is enabled (high) and both of the bank selection signals (BSn−1 and BSn+1) of the adjacent banks are disabled (low). However, the end banks (B
0
or B
15
) are set to an enbable state when a bank selection signal (BS
0
or BS
15
) of the corresponding bank (B
0
or B
15
) is enabled and bank selection signal (BS
1
in the case of end bank B
0
or BS
14
in the case of end bank B
15
) of the adjacent bank is disabled. This prevents two adjacent banks from being active simultaneously and having a conflict at a shared sense amplifier row (SA
0
to SA
16
).
Row decoders (DC
0
to DC
15
) are provided to correspond to banks (B
0
to B
15
), respectively. Each row decoder (DC
0
to DC
15
) can decode a row address signal RA provided by row address buffer
2
when the corresponding bank enable signal (BE
0
to BE
15
) becomes active. In this manner, a row decoder (DC
0
to DC
15
) can activate only the word line specified by the row address signal RA among the word lines in the corresponding bank (B
0
to B
15
).
Sense amplifier rows (SA
0
to SA
16
) are provided at each side of banks (B
0
to B
15
). Sense amplifier rows (SA
1
to SA
15
) can be shared between two adjacent banks (B
0
to B
15
). End sense amplifier rows (SA
0
and SA
16
) can be unshared. Each sense amplifier bank (SA
0
to SA
16
) can contain half as many sense amplifiers as there are bit line pairs in each bank (B
0
to B
15
). Within a bank (B
0
to B
15
) every other bit line pair can extend to be received
Fujima Shiro
Ishikawa Toru
Phan Trong
Walker Darryl G.
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