Static information storage and retrieval – Powering
Reexamination Certificate
2000-04-11
2001-02-13
Nelms, David (Department: 2818)
Static information storage and retrieval
Powering
C365S210130, C365S230060
Reexamination Certificate
active
06188628
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor storage device functioning as a random access memory (ROM), and more particularly, it relates to a measure to realize a RAM with small power consumption.
Recently, semiconductor devices, typically such as an LSI for use in portable equipment, have been developed to attain higher integration and smaller power consumption. Among the semiconductor devices, those such as a memory and a system LSI including a memory are desired to decrease the power consumption in a standby mode for waiting for data write and data read. In particular, in an LSI required for holding data in a memory for a long period of time with power supplied by a battery or the like, there is an earnest demand for reduce of a leakage current in the standby mode.
FIG. 13
is a block diagram for schematically showing the configuration of a semiconductor storage device disclosed in Japanese Laid-Open Patent Publication No. 7-254284, which is an example of the conventional measure to reduce power consumption. As is shown in
FIG. 13
, the conventional semiconductor storage device comprises a memory cell array
101
including memory cells
102
for storing data arranged in rows and columns; a word line WL extending along each row of the memory cell array
101
for making accesses to the memory cells
102
arranged in the row; a pair of bit lines BL and NBL extending along each column of the memory cell array
101
for inputting data in and outputting data from the memory cells
102
arranged in the column; a peripheral circuit
103
for controlling potentials of the word lines WL and the bit lines BL and NBL in order to write data in and read data from the memory cells
102
; a power voltage supply terminal
109
for supplying a power voltage VCC; a peripheral circuit power line
104
for connecting the power voltage supply terminal
109
to the peripheral circuit
103
; a peripheral circuit power switch
110
provided on the peripheral circuit power line
104
; and a memory cell array power line
105
for connecting the power voltage supply terminal
109
to the memory cell array
101
. The memory cell array power line
105
is directly connected to the power voltage supply terminal
109
with the peripheral circuit power switch
110
bypassed.
This semiconductor storage device is operated as follows:
In an operation mode where the semiconductor storage device conducts a write operation or a read operation, the peripheral circuit power switch
110
is placed in anon state (conducting state), so as to supply the power voltage VCC to the peripheral circuit
103
through the peripheral circuit power line
104
, thereby placing the peripheral circuit
103
in an activated state. At this point, since the memory cell array power line
105
is always supplied with the power voltage VCC, the memory cell array
101
is always in an activated state. Thereafter, specific word line WL and bit lines BL and NBL are selected by the peripheral circuit
103
in accordance with an externally input address, and a write operation or a read operation is carried out on a selected memory cell
102
.
On the other hand, in a standby mode where the semiconductor storage device keeps data in the memory cells without conducting a write operation and a read operation, the peripheral circuit power switch
110
is placed in an off state (non-conducting state), so as to cut off the power voltage VCC from the peripheral circuit power line
104
, thereby placing the peripheral circuit
103
in an inactivated state. Also in this case, the memory cell array power line
105
is always supplied with the power voltage VCC, so that the data held in the memory cell array
101
can be kept.
FIG. 12
is an electric circuit diagram of a generally used CMOS memory cell. In
FIG. 12
, reference numerals
120
and
121
denote load transistors of PMOS transistors, and reference numerals
122
and
123
denote drive transistors of NMOS transistors. Each of the load transistors
120
and
121
is supplied with the power voltage VCC through the memory cell array power line
105
, and each of the drive transistors
122
and
123
is supplied with a ground voltage VSS. Also, reference numerals
124
and
125
denote access transistors of NMOS transistors for receiving a signal on the word line WL at their gates. Each of the access transistors
124
and
125
is turned on/off in response to the signal on the word line WL, that is, an access signal, received at its gate, so as to control data write and data read to the bit lines BL and NBL.
Now, the function of the memory cell
102
will be described. The memory cell
102
holds a data by using a potential of a first node N
1
and a potential of a second node N
2
, which is an inverted potential of the potential of the first node N
1
. Specifically, a data held by the memory cell
102
is determined in accordance with the potential latching states in the first and second nodes N
1
and N
2
. When the potential of the first node N
1
is at a high level, the load transistor
121
is in an off state and the drive transistor
123
is in an on state, and hence, the potential of the second node N
2
is at a low level. Accordingly, the load transistor
120
is in an on state and the drive transistor
122
is in an off state, so that the first node N
1
can keep the potential at a high level and the second node N
2
can keep the potential at a low level. Therefore, by previously determining that, for example, a data held when the first node N
1
has a high potential and the second node N
2
has a low potential is “1” and that a data held when the first node N
1
has a low potential and the second node N
2
has a high potential is “0”, a one-bit data can be stored in the memory cell
102
.
In a read operation, a high potential is applied to the word line WL in accordance with an externally input address to select the memory cell
102
, and the access transistors
124
and
125
are turned on, so as to connect the first node N
1
to the bit line BL and connect the second node N
2
to the bit line NBL. Before this operation, the bit lines BL and NBL are precharged to a high potential, and hence, the potential of the first node N
1
kept at a high level is not varied while the potential of the second node N
2
kept at a low level is decreased because of a current flowing from the bit line NBL. A potential difference between the bit lines BL and NBL caused at this point is detected by a circuit (differential amplifier circuit) included in the peripheral circuit
103
, so as to be output as a data. When a data “1” is held, the potential of the bit line BL is at a high level and the potential of the bit line NBL is at a low level. When a data “0” is held, the potential of the bit line BL is at a low level and the potential of the bit line NBL is at a high level.
In a write operation, a high potential is applied to the word line WL in accordance with an externally input address to select the memory cell
102
, and the gate potentials of the access transistors are set to a high level. Accordingly, the access transistors
124
and
125
are turned on, so as to electrically connect the first node N
1
to the bit line BL and the second node N
2
to the bit line NBL. The bit lines BL and NBL are supplied with complementary potentials in accordance with input data. For example, in writing (overwriting) a data “0” in the memory cell
102
holding a data “1”, the bit line BL is supplied with a low potential and the bit line NBL is supplied with a high potential. Therefore, the potential of the first node N
1
connected to the bit line BL at a low potential level is decreased, so as to turn on the load transistor
121
and turn off the drive transistor
123
. As a, result, the potential of the second node N
2
undergoes a low to high transition. Therefore, the load transistor
120
is turned off and the drive transistor
122
is turned on, so that the potential of the first node N
1
can undergo a high to low transition.
In this manner, the supply of the power voltage
Ho Hoai V.
Matsushita Electric - Industrial Co., Ltd.
McDermott & Will & Emery
Nelms David
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