Semiconductor storage device

Details Semiconductor storage device Semiconductor storage device

2008-01-17

2009-08-18

Phung, Anh (Department: 2824)

Static information storage and retrieval

Floating gate

Multiple values

C365S185220

Reexamination Certificate

active

07577030

ABSTRACT:
A memory cell array has a plurality of multi-value memory cells arranged therein that can store information of two bits or more in one memory cell as a different page. In each of the data registers, an acceptable number setting register, which temporarily retains data read from the memory cell array, stores multiple acceptable numbers of data states corresponding to each state of threshold voltages of each of the pages in the multi-value memory cells. A selector selects, from the multiple acceptable numbers of data states, an acceptable number of data states for data retained in each of the data registers corresponding to each page of the multi-value memory cells. A comparator compares the number of data states retained in each of the data registers with the acceptable number of data states selected by the selector.

REFERENCES:
patent: 6856546 (2005-02-01), Guterman et al.
patent: 7184348 (2007-02-01), Crippa et al.
patent: 7457164 (2008-11-01), Ohta
patent: 2004/0062099 (2004-04-01), Hosono et al.
patent: 2004/0170056 (2004-09-01), Shibata et al.
patent: 2006/0117214 (2006-06-01), Sugiura et al.
patent: 2007/0297236 (2007-12-01), Tokiwa

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