Semiconductor stack structures and fabrication sparing methods u

Details Semiconductor stack structures and fabrication sparing methods u Semiconductor stack structures and fabrication sparing methods u

1995-04-27

1998-08-25

Niebling, John

Semiconductor device manufacturing: process

With measuring or testing

Packaging or treatment of packaged semiconductor

438109, H01L 2150

Patent

active

057982821

ABSTRACT:
Electronic semiconductor structures, and fabrication and sparing methods, each utilize an electrically programmable spare circuit incorporated with a multichip package. The programmable sparing capability in the multichip package is accomplished either with or without the inclusion of a spare chip(s). With a spare memory circuit, individual failed memory cells in the semiconductor chips of a stack can be functionally replaced by memory cells of the spare memory circuit subsequent to encapsulation and burn-in testing. With use of a spare chip, non-volatile sparing can occur subsequent to encapsulation and burn-in testing without physical rewiring of a wire bond connection. Specific details of alternate electronic semiconductor structures, and fabrication and sparing methods therefore, are set forth.

REFERENCES:
patent: 5008729 (1991-04-01), Wills et al.
patent: 5018104 (1991-05-01), Urai
patent: 5313424 (1994-05-01), Adams et al.

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