Synthetic resins or natural rubbers -- part of the class 520 ser – Synthetic resins – At least one aryl ring which is part of a fused or bridged...
Reexamination Certificate
2000-05-16
2003-12-02
Shosho, Callie (Department: 1714)
Synthetic resins or natural rubbers -- part of the class 520 ser
Synthetic resins
At least one aryl ring which is part of a fused or bridged...
C523S443000, C523S466000
Reexamination Certificate
active
06656996
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The present invention relates to a resin composition to be used for protecting semiconductor chips, and to a semiconductor device. In particular, the invention relates to a protective film, an under filler, a liquid sealant, a semiconductor-sealing resin composition containing a sealant, and also to a semiconductor device so sealed.
With the recent tendency toward downsized portable appliances, parts of semiconductor devices for those appliances are being downsized and thinned, and their quality is being much improved.
A conventional, resin-sealed semiconductor device comprises semiconductor chips and an interposer (lead frame), in which the chips except outer electrodes (pins) that are necessary for mounting the chips on a printed circuit board are sealed with a resin on both surfaces. Therefore, developing and improving a method of mounting semiconductor chips on a lead frame has heretofore been essentially targeted for downsized semiconductor devices.
For example, quad flat packages (QFP) with outer electrodes aligned on all four sides of each package have been developed from small outline J-lead packages (SOJ) with outer electrodes aligned only on two sides of each package; and lead on chip packages (LOC), with chips on inner lead pins for increasing the chip occupation in one package, have been developed from others with chips mounted on the stage of lead frames.
With the recent tendency toward downsized multi-pinned semiconductor devices (packages), in addition, ball grid array packages (BGA), pin grid array packages (PGA), land grid array packages (LGA) and the like, where outer electrodes are two-dimensionally spread on the outer surface of each package have been developed. In these, the number of pins can be increased without the pin-to-pin distance being reduced. However, even in BGA, the sizes of semiconductor devices shall be larger in some degree than that of semiconductor chips.
Accordingly, it is necessary to achieve more fully downsized, thinned and lightweight semiconductor devices and to develop semiconductor devices in which the areal size is reduced to that of semiconductor chips.
In that situation, some proposals have been made for making chip-size semiconductor devices. One is a flip chip bonding method of directly bonding chips to a printed circuit board with an under filler injected therebetween. However, the flip chip bonding method requires high-level packaging techniques of package makers and, in addition, increases the packaging costs, since the step of under filler injection takes much time.
Another method proposed for chip-size semiconductor devices comprises sealing semiconductor chips all at one time in a wafer, followed by cutting the thus-sealed wafer into individual chip-size semiconductor devices.
Semiconductor-sealing resin compositions to be used for fabricating such multi-pinned, downsized and thinned semiconductor devices generally comprise an organic resin with an inorganic filler therein. For preparing the resin compositions of such composite materials, the two components are wetted with each other by shear stress to ensure the strength of the composite materials. Wetting them may be effected in Banbury mixers, kneaders, extruders, roll mills or the like, in which, however, the sealing resins are often contaminated with metal impurities derived from tool abrasion. If multi-pinned, downsized and thinned semiconductor devices are sealed with resin compositions contaminated with such metal impurities, they will be short-circuited in some extreme cases and their reliability will lower. Thus, high-tech semiconductor devices (packages) fabricated by the use of conventional sealing resins will often lose reliability.
Moreover, in downsized and thinned semiconductor devices, the resin composition flow space is reduced, and, in addition, the mold cavity inlet for the resin composition flow will be narrowed and thinned. If downsized and thinned semiconductor devices are fabricated by the use of a resin composition contaminated with metal impurities in a mode of transfer molding, the mold cavity inlet will be clogged with the impurities, often bringing about molding failure. If the mold cavity inlet is clogged with such impurities, the molding operation must be stopped every time and productivity is greatly lowered. Summarizing, downsizing semiconductor devices is confronted with many difficulties in point of productivity.
SUMMARY OF THE INVENTION
The present invention is directed to an improved, semiconductor device-sealing resin composition, with which stable and reliable semiconductor devices can be fabricated, and also to a semiconductor device fabricated by the use of the composition.
The semiconductor-sealing resin composition of the invention contains a filler (A) of spherical fused silica having a maximum particle size of 45 &mgr;m or less, and may contain metal impurities having a particle size of 53 &mgr;m or less.
The semiconductor device of the invention is sealed with a resin composition which contains a filler (A) consisting essentially of spherical fused silica having a maximum particle size of 45 &mgr;m or less and may contain metal impurities having a particle size of 53 &mgr;m or less.
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Kawahara Toshimi
Mieda Tetsuya
Takigawa Yukio
Tanaka Masayuki
Tsutsumi Yasuaki
Piper Rudnick LLP
Shosho Callie
Sumitomo Bakelite Co. Ltd.
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