Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – With pn junction isolation
Patent
1999-04-19
2000-02-08
Jackson, Jr., Jerome
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
With pn junction isolation
257404, 257409, 257488, 257490, 257536, 257537, 257547, H01L 2900
Patent
active
060230924
ABSTRACT:
A resistor on a semiconductor wafer comprising a silicon substrate, a first doped layer in a predetermined area on the silicon substrate, a second doped layer within a predetermined area of the first doped layer, a dielectric layer above the first and second doped layers on the silicon substrate, a passivation layer on the dielectric layer, and a conducting layer between the dielectric layer and the passivation layer. The silicon substrate contains dopants that characterize it as an n-type (or p-type) semiconductor. The first doped layer functioning as a resistor layer is a p-type (or n-type) semiconductor and forms a first pn-junction at its interface with the silicon substrate to prevent electrical leakage. The second doped layer is a n-type (p-type) semiconductor and forms a second pn-junction at its interface with the first doped layer that prevents electrical leakage. The passivation layer has a plurality of charges at fixed positions. The conducting layer prevents the electric field generated by the charges of the passivation layer from reducing the breakdown voltages of the first and second pn-junctions at their intersections with the surface of the dielectric layer.
Hsu Winston
Jackson, Jr. Jerome
Ortiz Edgarlo
United Microelectronics Corp.
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