Static information storage and retrieval – Powering – Data preservation
Reexamination Certificate
2001-02-26
2002-04-30
Le, Vu A. (Department: 2818)
Static information storage and retrieval
Powering
Data preservation
C365S226000, C365S189050
Reexamination Certificate
active
06381189
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to technique for reducing power consumption during standby time of a CMOS semiconductor logic integrated circuit.
BACKGROUND OF THE INVENTION
In the present invention, standby time of an integrated circuit refers to a time period of a sleeping status or a non-operating status, in which the integrated circuit waits for input or occurrence of a certain predicted signal and shifts to a next predicted operation.
In the case of an electronic in which standby time makes up a large proportion relative to an operating time and a battery is used as a power voltage supply source, it has become a common practice to suspend almost all the operations of the integrated circuit and an operating clock of its surrounding circuit so as to cut the power consumption, thereby maximizing the life expectancy of the battery.
Further, in recent years, longer life expectancy of a battery has become increasingly important as a customers' criterion for purchasing a portable electronic and a goal of competitive performance.
Power leakage current of a CMOS semiconductor logic integrated circuit is categorized into leakage on a depletion layer for element separation, off leakage on a transistor channel, and leakage between wirings. In a time when a transistor has a minimum gate length of 1 &mgr;m or more, off leakage current of a transistor channel is smaller than reverse bias leakage current of the depletion layer, resulting in no problem.
However, at the present time of sub &mgr;m and deep sub &mgr;m, off leakage current of a transistor channel cannot be negligible as compared with other leakage currents.
This is why power consumption rises with increasing power leakage current during standby time of an MOS semiconductor logic integrated circuit.
In recent years, power consumption is likely to increase because of a larger number of transistors per chip of an integrated circuit, higher performance of an electronic, and the enhanced speed of an operating clock with faster response. Additionally, the demand for an electronic is shifted from a stationary electronic provided for each family to a portable electronic for each person, so that it is necessary to increase the life expectancy of a battery installed into an electronic. Furthermore, because of the need for a smaller and a thinner model, an electronic is downsized such that a permissible loss heat packaging capacity of an integrated circuit package is further limited and power consumption of that circuit is largely reduced under operation.
The most effective means for solving the above problem is to lower operating source voltage, which can reduce power consumption in inverse proportion nearly to the second power.
Therefore, in order to realize a low source voltage and a high-speed integrated circuit, the designer has set a gate threshold voltage of a transistor, which is installed into a semiconductor, at a voltage decreasing proportionally to source voltage, even though a channel-off leakage current is sacrificed to some extent.
However, a channel-off leakage current of the transistor is determined by semiconductor diffusion parameters such as a diffusion coefficient of the channel, a thickness of a gate oxide film, and a gate threshold voltage. Thus, under present circumstances, after the completion of the integrated circuit, the designer who installs the integrated circuit on the market into the electronic does not have any effective means for reducing power consumption increased by leakage current.
For this reason, the following measure (1-1) or (1-2) has been conventionally taken as a means for reducing power consumption during standby time.
(1-1) During standby time, memory information is held, which is necessary for continuing the operation of an integrated circuit, and a minimum source voltage is applied during standby time so as to immediately make a shift to the following operating status without formatting or resetting.
(1-2) In order to reduce a channel-off leakage current of the transistor, a high gate threshold voltage is applied during standby time to deepen a back gate bias voltage.
However, the use of the above means causes the following disadvantage (1-3) or (1-4).
(1-3) In case of (1-1), with a low source voltage applied during standby time, it is not possible to attain a design target value of power consumption during standby time because of quite too large a number of transistors provided in the integrated circuit.
(1-4) In case of (1-2), during standby time, a gate threshold voltage is increased higher than that of the operating status. Hence, in a CMOS semiconductor integrated circuit, a source voltage supply circuit is installed to set a back gate bias voltage higher than a source voltage on a P-channel transistor and lower than a ground voltage on an N-channel transistor, thereby increasing the cost.
Moreover, in case of (1-4), a back gate bias potential of each transistor is not direct-coupled to a source output with low impedance but is coupled to a high-impedance source output of a built-in source voltage supply circuit, which is less likely to incorporate a large-capacity capacitor for reducing power impedance. Thus, a latch-up withstand voltage is lowered by a parasitic transistor in the integrated circuit.
In order to lower the impedance of the internal source voltage supply circuit, it is necessary to append the source output on an external terminal of the integrated circuit and to externally connect a large-capacity bypass capacitor thereon.
Therefore, (1-3) is disadvantageous because the means is useless for reducing power consumption during standby time. (1-4) is disadvantageous because the cost is increased by adding the source voltage supply means.
In order to reduce power consumption during standby time of the CMOS semiconductor integrated circuit, the most effective means is to interrupt source voltage on a circuit part during standby time, which does not cause any problems in a subsequent resetting.
As for a timing function provided in an electronic, it is necessary to always apply source voltage regardless of standby time or operating time, because ticking is always required.
However, regarding a standby function of a mobile phone, a phone is in a standby status and its operation can be suspended to reduce the consumption of a battery source capacity, except for when the presence of an incoming call to its telephone number is intermittently confirmed at a fixed time interval.
In general, the integrated circuit is configured by the connection of a memory circuit, which always needs to store information for a continuous operation, and combinational logic gates, which do not have to store the information.
In the memory circuit, regarding register elements and memory elements (hereinafter, these elements are referred to as temporary memory elements) in which stored information is erased upon interruption of source voltage, if a means is adopted for preventing stored information from being erased, the object of the present invention can be attained even in the case where source voltage is interrupted on a logic gate element of the combinational logic gates, a buffer element, a permanent memory element for holding stored information under the interruption of source voltage, an analog function element, or other elements (hereinafter, these elements are referred to as elements other than the temporary memory elements).
Namely, in this case, in order to reduce power consumption during standby time, a proposal is made that a source voltage be applied only to the following (2-1) and (2-2) as the fewest elements having to receive source voltage in the integrated circuit during standby time and source voltage supply be totally suspended on the other elements except the temporary memory elements.
(2-1) All the temporary memory elements.
(2-2) Elements other than the temporary memory elements of the integrated circuit that make electrical connection with external devices of the integrated circuit and need to maintain electrical exchange of information or a controlling
Le Vu A.
Matsushita Electric - Industrial Co., Ltd.
Parkhurst & Wendel LLP
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