Semiconductor recessed mask interconnect technology

Details Semiconductor recessed mask interconnect technology Semiconductor recessed mask interconnect technology

2000-11-01

2003-12-02

Coleman, W. David (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

Reexamination Certificate

active

06657305

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to the use of a recessed mask structure to prevent localized high electrical fields at intersections with resulting lower electrical breakdown, in very small dimension semiconductor devices such as would be encountered in high speed and high density integrated circuit applications and chip interconnect structures with fine metal features and low dielectric constant insulators.
BACKGROUND OF THE INVENTION
In the miniaturizing of semiconductor devices, as the spacing and dimensions approach the below 150 nanometer range, dimensional tolerances become very small and abrupt physical discontinuities such as interfaces between different materials produce high electrical fields that in turn result in enhanced leakage and breakdown. Further, at such small dimensions, different materials than commonly used heretofore, with different properties such as lower dielectric constant (k), are being found attractive for use in lowering such device parameters as line to line capacitance, reducing cross talk noise and power dissipation. Still further, the different materials in turn behave differently in processing.
An illustration of many of the considerations involved in developing integrated circuit interconnect structures and processes where the dimensions are in the sub 250 nanometer range appears in the 7 page technical article titled “Pursuing The Perfect Low-k Dielectric”, by Laura Peters, and appearing in Semiconductor International Magazine in the Sep. 1, 1998 issue.
There is a clear need in the art for a capability that will operate to provide relaxation of limitations and to reduce complexity of the situations that are being encountered in providing interconnect structures and in the fabrication thereof in the sub 250 nanometer dimension range.
SUMMARY OF THE INVENTION
A metal plus low dielectric constant (low-k) interconnect structure is provided for a semiconductor device wherein adjacent regions in a surface separated by a dielectric have dimensions in width and spacing in the sub 250 nanometer range, and in which reduced lateral leakage current between adjacent metal lines, and a lower effective dielectric constant than a conventional structure, is achieved by the positioning of a differentiating or mask member that is applied for the protection of the dielectric in subsequent processing operations, at a position below a surface to be planarized, where there will be a lower electric field. The mask position, is in the range of about 0.5 to 20 nanometers, with 5 nanometers being preferred, below the surface to be planarized, at a location where the surfaces of the regions separated by the dielectric are undisturbed and have complete integrity. The invention is particularly useful in the damascene type device structure in the art wherein adjacent conductors lined with an electrically conductive and diffusion barrier film are disposed in thin trenches in an intralevel dielectric material (WLD), connections are made to levels above and below diffusion barrier film are disposed in thin trenches in an intralevel dielectric material (ILD), connections are made to levels above and below through metal filled vias in the ILD, masking is employed both to protect the dielectric material between conductors during processing operations, and to assist in patterning those trenches within the interlevel dielectric material. A dielectric cap is also usually applied over the surfaces of the metal lines and the masking layer, to further separate successive levels of metal wiring through metal filled vias in the ILD, masking is employed both to protect the dielectric material between conductors during processing operations, and to assist in patterning those trenches within the interlevel dielectric material. A dielectric cap is also usually applied over the surfaces of the metal lines and the masking layer, to further separate successive levels of metal wiring.


REFERENCES:
patent: 6153935 (2000-11-01), Edelstein et al.
patent: 6207556 (2001-03-01), Hsu
patent: 6245665 (2001-06-01), Yokoyama
patent: 6245683 (2001-06-01), Liu
patent: 6294835 (2001-09-01), Dalal et al.
patent: 6329701 (2001-12-01), Ngo et al.
“Pursuing the Perfect Low-K Dielectric”, Laura Peters, Semiconductor International Magazine, Sep. 1, 1998 7 pages.

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