Semiconductor read only memory

Static information storage and retrieval – Format or disposition of elements

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Details

365104, 365182, G11C 1300, G11C 1140

Patent

active

052950921

ABSTRACT:
A semiconductor read only memory of this invention includes a plurality of word lines disposed in parallel. The read only memory has a plurality of units. Each of the plurality of units includes: a first bit line which crosses the word lines; a plurality of first virtual ground lines disposed substantially in parallel with the first bit line, each of the plurality of first virtual ground lines having a first end and a second end; a plurality of second virtual ground lines corresponding to the plurality of first virtual ground line, each of the plurality of second virtual ground lines having a first end and a second end; second bit lines, each provided between two adjacent ones of the plurality of second virtual ground lines, each of the second bit lines having a first end and a second end; memory cell columns, each constituted by a plurality of memory cells connected in parallel between one of the second virtual ground lines and one of the second bit lines adjacent thereto; and bank select switching elements for selecting one of the memory cell columns. In the read only memory, the second ends of the plurality of first virtual ground lines are respectively connected to the second ends of the second virtual ground lines, and the first ends of the second bit lines are respectively connected to the bank select switching elements.

REFERENCES:
patent: 5031139 (1991-07-01), Sinclair
Ser. No. 07/781,630 to Yasuhiro Hotta dated Oct. 22, 1991.
Okada, M., et al., "16Mb ROM Design Using Bank Select Architecture", 1988 Symposium On VLSI Circuits, Digest of Technical Papers, Aug. 22-25, 1988, Tokyo, pp. 85-86.

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