Semiconductor random access memory device having shared sense am

Static information storage and retrieval – Addressing – Plural blocks or banks

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36518907, 36518908, G11C 1504

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active

053011627

ABSTRACT:
A random access memory device has memory cell blocks, row address decoders respectively associated with the memory cell blocks, sense amplifier circuit arrays each shared between two of the memory cell blocks, and a column selecting unit for transferring a data bit from one of the sense amplifier circuit arrays to an output data buffer circuit, a flag generating unit for producing flag signals indicative of memory cell blocks supplying the data bits presently stored in the sense amplifier circuit arrays, and an address discriminating unit operative to examine block and row addresses supplied from the outside thereof to see whether or not an accessed data bit has been already stored in the sense amplifier circuit arrays, thereby allowing the shared sense amplifier circuit arrays to serve as a cache memory.

REFERENCES:
patent: 4675850 (1987-06-01), Kumanoya et al.
patent: 5226009 (1993-07-01), Arimoto
patent: 5226139 (1993-07-01), Fujishima et al.
H. Niijima et al., "QRAM-Quick Access Memory System", 1990 IEEE, pp. 417-420.
Nikkei Electronics, Mar. 30, 1992, No. 550, pp. 202-203, and a partial translation.
"Using the page mode of dynamic RAMs to obtain a pseudo cache", Microprocessors and Microsystems, vol. 11, No. 9, Nov. 1987, pp. 469-473.

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