Semiconductor protection circuit having both positive and negati

Details Semiconductor protection circuit having both positive and negati Semiconductor protection circuit having both positive and negati

1987-06-15

1988-06-07

Pellinen, A. D.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361 90, 361 86, 361 11, 357 2313, H02H 324

Patent

active

047500786

ABSTRACT:
An input protection circuit is provided which prevents positive and negative voltages significantly higher than a supply voltage potential from damaging operational circuitry connected to an input terminal. A bipolar transistor has current conducting electrodes connected between the supply voltage and the input terminal. A first MOS transistor is coupled to the bipolar transistor for selectively eliminating a forward biased junction between the base and collector of the bipolar transistor in response to the sign and magnitude of an input signal. A second MOS transistor is coupled to the bipolar transistor for selectively eliminating a forward biased junction between the base and emitter of the bipolar transistor in responses to the sign and magnitude of the input signal.

REFERENCES:
patent: 4302791 (1981-11-01), Buchanan et al.
patent: 4484244 (1984-11-01), Avery
patent: 4633283 (1986-12-01), Avery
patent: 4698720 (1987-10-01), Finaurini
patent: 4704654 (1987-11-01), Aberle et al.

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