Semiconductor protection circuit and semiconductor protection de

Details Semiconductor protection circuit and semiconductor protection de Semiconductor protection circuit and semiconductor protection de

1994-09-12

1997-02-18

Gaffin, Jeffrey A.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

361111, H02H 900

Patent

active

056046553

ABSTRACT:
A semiconductor protection circuit for protecting an internal circuit from a surge voltage comprises a depletion type PMOS transistor in which its drain is connected to the input/output terminal of the internal circuit. The control terminal is connected to the gate of the PMOS transistor. The control terminal applies a high voltage or low voltage to the gate in accordance with the ON or OFF state of the power of the internal circuit. When the high or low voltage is applied to the gate, the channel of the PMOS transistor is rendered non-conductive or conductive, respectively. The source of the PMOS transistor is grounded via a PN diode and a junction capacitor provided parallel. When a negative surge voltage is applied, the diode is rendered conductive, thereby protecting the internal circuit. When a positive surge voltage is applied, the diode is broken down, thereby protecting the internal circuit. The surge voltage is made small by the capacitor's static capacitance. When the control terminal is in a high potential state, the channel of the PMOS transistor disappears. Therefore, the internal circuit is released from the diode and capacitor. Consequently, during operation of the internal circuit, the parasitic capacitance at the input/output terminal is reduced.

REFERENCES:
patent: 4385337 (1983-05-01), Asano et al.

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