Semiconductor protecting apparatus and method for preventing des

Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means

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361 18, 361 86, 361 91, H02H 902

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active

053791746

ABSTRACT:
In a semiconductor integrated circuit device including a substrate bias voltage generating circuit supplying a substrate bias voltage to internal circuit performing original functions and a substrate where the internal circuit is formed, an N channel MOS transistor is provided between the internal circuit and power supply pad receiving an external voltage Vcc for driving the circuit. The transistor is controlled such that it is rendered conductive when substrate potential V.sub.SB is higher than the threshold voltage of MOS transistor and non-conductive when potential V.sub.SB is lower than the threshold voltage. Since supply of power supply voltage Vcc to the internal circuit is interrupted if latch-up is caused in the internal circuit and substrate potential V.sub.SB rises, internal circuit is immediately freed from the latch-up state even if latch-up is caused. Therefore, the internal circuit is protected from being heated or destructed by a current due to the latch-up.

REFERENCES:
patent: 4594633 (1986-06-01), Townsend et al.
patent: 4791316 (1988-12-01), Winnerl et al.

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