Semiconductor producing apparatus and temperature control...

Details Semiconductor producing apparatus and temperature control... Semiconductor producing apparatus and temperature control...

1999-10-06

2002-12-17

Patel, Ramesh (Department: 2121)

Data processing: generic control systems or specific application

Specific application, apparatus or process

Product assembly or manufacturing

C700S117000, C700S028000, C700S029000, C700S030000, C700S041000, C700S042000, C702S099000, C702S130000, C702S136000, C219S483000, C219S486000, C219S494000, C219S501000, C438S660000, C438S795000, C438S799000

Reexamination Certificate

active

06496749

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor producing apparatus equipped with a heat treatment device such as a diffusion devices a CVD, etc., capable of heat-treating semiconductor wafers in batches, and it also relates to a temperature control method for such a semiconductor producing apparatus.
2. Description of the Related Art
In a heat treatment device for a semiconductor producing apparatus such as a diffusion device, a CVD, etc., having an electric furnace for example, it is necessary to maintain the temperature of the electric furnace at an appropriate temperature, or make the interior of the electric furnace follow a dictated temperature change. Such a temperature control is required to have high precision or high performance with respect to compensation against external disturbances, and followability against a change in a target temperature. Conventionally, a control method as illustrated in
FIG. 28
for example has been used for the temperature control on such a heat treatment device.
The control method of
FIG. 28
employs an adder
1
having a target temperature input end IN and outputting a deviation or diference between a target temperature inputted to the target temperature input end IN and a detected temperature (controlled quantity or variable) from a heat treatment furnace
3
to be described later, a PID adjuster in the form of a PID adjustment section
2
provided at an output side of the adder
1
for performing PID calculations (e.g., proportioning, integrating and differentiating calculations) based on an output of the adder
1
and outputting a manipulated quantity or variable for the heat treatment furnace or device
3
thus calculated, and the heat treatment furnace
3
provided at an output side of the PID adjustment section
2
and having an input end a for receiving an output of the PID adjustment season
2
as a manipulated variable and an output end h for outputting the detected temperature (controlled variable), whereby the detected temperature (controlled variable) outputted from the output end b of the heat treatment furnace
3
can be controlled to a desired value.
The PID adjustment section
2
may include, as required, a known function of coping with integration anti-wind-ups or bumpless technique. The heat treatment furnace
3
among various components of
FIG. 28
is schematically configured as illustrated in FIGS.
29
(
a
) for example. Specifically, the heat treatment furnace
3
of FIG.
29
(
a
) includes an electric furnace
31
having an input end a for inputting a manipulated quantity or variable, an output end b for outputting a controlled variable and an introduction port through which semiconductor wafers are to be introduced or loaded into the electric furnace
31
, a boat
32
for holding the semiconductor wafers in the electric furnace
31
, a cap
33
for closing the introduction port of the electric furnace
31
and supporting the boat
32
, a heater
34
adapted to be supplied, though not shown, with electric power in response to a control signal from the input end a to heat the interior of the electric furnace
31
, and a temperature sensor
35
for detecting the temperature of the interior of the electric furnace
31
and outputting the detected temperature to the output end b, whereby the interior temperature of the electric furnace
31
is controlled to follow or maintain a specific temperature pattern, thus chemically processing the semiconductor wafers held by the boat
32
.
Also, for the purpose of temperature control, the electric furnace
31
as representatively illustrated in FIGS.
20
(
a
) and
29
(
b
) has a heating element divided into a plurality of heating zones to each of which electric power is supplied independently of each other to control the temperature thereof. For example, in the case of FIG.
29
(
a
), the heating element takes, if divided into four zones, such a configuration as shown in FIG.
30
.
Similar to FIG.
29
(
a
), the heat treatment furnace
3
A of
FIG. 30
includes, as its constructional components, an electric furnace
31
, a boat
32
, a cap
33
and a heater
44
. The heater
44
, being divided into four sections, is constructed such that it is provided with four manipulated variable input ends a
1
through a
4
, a temperature sensor
45
for measuring the temperatures of the respective four-divided zones, and four controlled variable output ends b
1
through b
4
corresponding to the four zones a
1
through a
4
, respectively.
In the following description, a collection of components provided in a route extending from the manipulated variable input end a
1
to the controlled variable output end b
1
may be designated at zone
1
, and similarly, another collection of components in another route from a
2
to b
2
, a further collection of components in a further route from a
3
to b
3
and so on may be respectively designated at zone
2
, zone
3
and so on.
In the case of a heat treatment furnace of the configuration having a plurality of heating zones, for example four-divided zones as illustrated in
FIG. 30
, there has often been used a control scheme in which the configuration of
FIG. 28
is simply formed into a plurality of heating zones in parallel with each other, as illustrated in FIG.
31
. The heat treatment furnace
3
A among the components of
FIG. 31
has four manipulated variable input ends at through a
4
and four manipulated variable output ends b
1
through b
4
, as shown in FIG.
30
. Here, reference symbols
1
-
1
through
1
-
4
designate a plurality of parallel adders, and reference symbols
2
-
1
through
2
-
4
designate a plurality of parallel PID adjustment sections.
The heat treatment furnaces as illustrated in
FIGS. 30 and 31
carry out a process treatment in accordance with a temperature control procedure as shown in FIGS.
32
(
a
) and
32
(
b
) for example.
Here, a description will be made of an example of the process treatment carried out by such a conventional heat treatment furnace described above, while referring to FIGS.
32
(
a
) and
32
(
b
). FIG.
32
(
a
) is a flowchart illustrating such an example of heat treatment carried out by the above-mentioned heat treatment furnace, and FIG.
32
(
b
) schematically shows the temperature of the heat treatment furnace during the heat treatment. In FIG.
32
(
b
), symbols designate processings indicated by the same symbols in FIG.
32
(
a
).
In FIG.
32
(
a
), a step S
101
is to maintain and stabilize the temperature in the interior of the electric furnace
31
at a relatively low temperature T
0
. In step S
101
, the boat
32
has not yet been introduced into the electric furnace
31
. A step
8102
is to introduce or load the boat
32
holding semiconductor wafers into the electric furnace
31
. As a result of the boat
32
having been loaded into the electric furnace
31
, due to the fact that the semiconductor wafers are generally lower in temperature than the temperature T
0
of the electric furnace
31
, the temperature of the electric furnace
31
temporally becomes lower than the temperature T
0
, but it is restored and stabilized to that temperature T
0
in a certain period of time under the above-described temperature control.
A step S
103
is to gradually raise the temperature of the electric furnace
31
from the temperature T
0
to a temperature T
1
, which is suitable for a process treatment such as a film forming treatment on the semiconductor wafers (e.g., forming a thin layer or film on each semiconductor wafer). A step S
104
is to maintain and stabilize the Interior temperature of the electric furnace
31
at the temperature T
1
in order to perform a process treatment on the semiconductor wafers. A step S
105
is to gradually lower, after the process treatment having been finished, the temperature of the electric furnace
31
from the temperature T
1
to the relatively lower temperature T
0
. Thereafter, a step S
106
is carried out which is to take the boat
32
holding the process-treated semiconductor wafers out of th

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