Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-08-04
2001-09-11
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S396000, C438S260000, C438S255000, C438S239000, C257S309000, C257S296000, C257S308000
Reexamination Certificate
active
06287935
ABSTRACT:
TECHNICAL FIELD
This invention relates to semiconductor processing methods of forming hemispherical grain polysilicon layers, methods of forming capacitors, and capacitors.
BACKGROUND OF THE INVENTION
As integration density of semiconductor memory devices increases, the separation between adjacent memory cells decreases. Such decrease in separation can cause shorting between adjacent devices.
FIG. 1
illustrates exemplary problems. A semiconductor wafer fragment
10
comprises a bulk substrate
12
having diffusion regions
15
formed therein. Diffusion regions
15
can be part of transistor constructions. Conductive plugs
14
are electrically connected to regions
15
and extend to capacitor constructions
13
.
Capacitor constructions
13
comprise a storage node
20
, which in the shown example is a hemispherical grain polysilicon (HSG) layer. A dielectric layer
22
is provided over the HSG layer
20
and a conductive layer
24
is formed over dielectric layer
22
. Conductive layer
24
defines a capacitor plate for capacitor constructions
13
.
Close spacing of adjacent capacitor constructions
13
can inhibit conformal forming of layers
22
and
24
, and lead to voids
26
being formed between adjacent capacitor constructions
13
. Such voids
26
can undesirably alter dielectric properties at various regions of capacitor constructions
13
relative to other regions of the capacitor constructions
13
.
Another problem that can be caused by the close spacing of capacitor constructions
13
is short circuiting between adjacent devices.
Either of the above-discussed problems can detrimentally affect the performance of the memory cells. Accordingly, it is desired to develop new methods of forming conductive devices, and in particular, it is desired to develop new methods of forming capacitor constructions.
SUMMARY OF THE INVENTION
In one aspect of the invention, an amorphous layer of silicon is provided which has a gradient of thickness variation. The amorphous layer of silicon is transformed into a hemispherical grain polysilicon layer that has varying grain size therein.
In another aspect of the invention, an opening is formed in a material and the opening has inwardly sloped walls. A plurality of hemispherical grain polysilicon layers are formed within the opening and the hemispherical grain polysilicon layers extend from a lower portion of the opening to an upper portion. At least one hemispherical grain polysilicon layer has a grain size which increases at the lower portion of the opening relative to a grain size of the hemispherical grain polysilicon layer at the upper portion of the opening.
In still another aspect of the invention, a material is provided and has an upper surface and inwardly tapered openings. A first electrically conductive electrode layer is formed within the openings and the first electrode layer includes hemispherical grain polysilicon. The first electrode layer has terminal ends that form an upper surface proximate the upper surface of the material. The hemispherical grain polysilicon has a grain size gradient defined by a smaller grain size at the terminal ends and a larger grain size beneath the upper surface. An electrically insulative layer is formed over the first electrode layer and a second electrically conductive electrode layer is formed over the electrically insulative layer.
In yet another aspect of the invention, a material with an opening therein has a first electrically conductive electrode layer of hemispherical grain polysilicon within the opening. The hemispherical grain polysilicon has a portion proximate an upper surface of the material. The hemispherical grain polysilicon has a grain size gradient defined by a smaller grain size at the portion proximate the upper surface and a larger grain size at another portion below the portion proximate the upper surface. An electrically insulative layer extends over the first electrode layer and a second electrically conductive electrode layer extends over the electrically insulative layer.
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Micro)n Technology, Inc.
Smith Matthew
Wells, St. John, Roberts Gregory & Matkin P.S.
Yevsikov V.
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