Semiconductor device manufacturing: process – Gettering of substrate – By implanting or irradiating
Reexamination Certificate
2001-03-14
2002-10-22
Chaudhuri, Olik (Department: 2813)
Semiconductor device manufacturing: process
Gettering of substrate
By implanting or irradiating
C438S484000
Reexamination Certificate
active
06468883
ABSTRACT:
TECHNICAL FIELD
This invention relates to semiconductor processing methods of forming contact openings, methods of forming electrical connections and interconnections, and integrated circuitry comprising such contact openings and electrical connections and interconnections.
BACKGROUND OF THE INVENTION
Referring to
FIGS. 1 and 2
, a semiconductor wafer fragment is indicated generally at
10
and comprises a semiconductive substrate
12
. In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. Substrate
12
comprises a field oxide region
13
having an outer surface
14
(
FIG. 2
) over which a plurality of conductive runners or conductive lines
16
,
18
, and
20
are formed. The illustrated conductive lines or runners include conductive portions and insulative portions. Exemplary conductive portions are constituted, in this example, by a respective polysilicon layer
22
and an overlying silicide layer
24
. The insulative portions of the runners or lines are constituted by respective overlying caps
26
and associated sidewall spacers
28
. Exemplary materials for the insulative portions include oxides and nitrides.
An insulative layer
30
such as borophosphosilicate glass is formed over runners
16
,
18
, and
20
and a contact opening
32
is formed through a masked etch of layer
30
to outwardly expose a portion of silicide layer
24
. Thereafter, conductive material such as conductively doped polysilicon is formed within contact opening
32
to provide a conductive contact
34
to conductive line
18
. A metal layer
36
is provided thereover to form an electrical connection with conductive line
18
.
A typical practice within the semiconductor industry is to provide a conductive line or runner with a widened landing pad in order to accommodate mask misalignments when contact openings are formed. An exemplary widened landing pad is shown in
FIG. 1
at
38
and
FIG. 2
by area A. By having a widened landing pad, contact opening
32
can shift left or right some distance relative to the position shown in
FIGS. 1 and 2
without making undesirable contact with the substrate. For purposes of the ongoing discussion, landing pad
38
includes the conductive and insulative portions of conductive line
18
; and the conductive portions of conductive line
18
define a contact pad with which electrical communication is desired. Accordingly, in the illustrated example a contact pad is defined by polysilicon layer
22
and silicide layer
24
of conductive line
18
. The contact pad defines a target area A inside of which it is desirable to form a contact opening. An electrical connection through contact opening
32
can be formed anywhere within target area A and still effectively make a desirable connection with the conductive contact pad. Hence, the target area tolerates a contact opening mask misalignment on either side of the illustrated and desired contact opening
32
. A tradeoff for improved mask misalignment tolerance is a reduction in wafer real estate available for supporting conductive lines and other integrated circuitry components. This is due largely in part to the increased area which is occupied by the widened landing pad
38
. This also adversely impacts the conductive line spacing such that desired minimum spacing adjacent conductive lines is not achieved. Hence, integrated circuitry cannot be packed as densely upon a wafer as is desirable when the widened landing pads are used.
This invention grew out of concerns associated with enhancing the efficiency with which wafer real estate is used to support integrated circuitry. This invention also grew out of concerns associated with improving the methods and structures through which contact is made relative to conductive lines.
SUMMARY OF THE INVENTION
Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed. In the former instance and in accordance with one aspect, such plug(s) can include a portion which overlaps with the contact pad of the associated conductive line.
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F. White et al., “Damascene Stud Local Interconnect in CMOS Technology,” IEEE Technical Digest of the 1992 International Electron Devices Meeting, pp. 301-304 (1992).*
“Merriam Webster's Collegiate Dictionary—Tenth Edition”, ©1996, p. 895, definition of plug.
Chaudhuri Olik
Micro)n Technology, Inc.
Smoot Stephen W.
Wells St. John P.S.
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