Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-08-30
2002-05-28
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C257S306000
Reexamination Certificate
active
06395613
ABSTRACT:
TECHNICAL FIELD
This invention relates to semiconductor processing methods of forming a plurality of capacitors on a substrate, bit line contacts and method of forming bit line contacts.
BACKGROUND OF THE INVENTION
Circuit devices fabricated on or over semiconductor wafers typically undergo one or more photolithographic steps during formation. During such photolithographic steps, device features can be etched using conventional techniques. The spacing between such devices is important because often times adjacent devices must be electrically isolated from one another to avoid unwanted electrical interconnections.
One of the limitations on device spacing stems from limitations inherent in the photolithographic process itself. In the prior art, devices are generally spaced only as close as the photolithographic limit will permit.
By way of example and referring to
FIGS. 1 and 2
, a semiconductor wafer fragment
25
includes a substrate
29
atop which a material
28
is provided. A plurality of patterned masking layers
26
are formed atop the material
28
.
Referring to
FIG. 3
, the material
28
is anisotropically etched through the patterned masking layers
26
to form lines
30
atop the substrate
29
. As shown, individual lines
30
have respective widths L
1
which constitute the minimum photolithographic feature size available for a line. Typically, a separation S
1
separates adjacent lines
30
across the substrate as shown. Such dimension is typically only slightly larger than L
1
but could be the same as L
1
. The term “pitch” as used herein is intended to be in its conventional usage, and is defined as the distance between one edge of a device and the corresponding same edge of the next adjacent device. Accordingly and in the illustrated example, the pitch P
1
between adjacent lines
30
(i.e., from the left illustrated edge of one line
30
to the left illustrated edge of the next immediately adjacent line
30
) is equal to the sum of L
1
and S
1
.
As integrated circuitry gets smaller and denser, the need to reduce spacing dimensions or pitch, such as S
1
and P
1
, becomes increasingly important. This invention grew out of the need to reduce the size of integrated circuits, and particularly the need to reduce spacing dimensions and pitches between adjacent devices over a semiconductor wafer.
SUMMARY OF THE INVENTION
The invention includes semiconductor processing methods and related integrated circuitry in which a plurality of patterned device outlines are formed over a semiconductor substrate. Electrically insulative partitions or spacers are then formed on at least a portion of the patterned device outlines, after which a plurality of substantially identically shaped devices are formed relative to the patterned device outlines. Individual formed devices are spaced from at least one other of the devices by a distance substantially no more than a width of one of the electrically insulative spacers.
According to one aspect of the invention, capacitors are formed. In one embodiment, a pair of adjacent capacitor containers are formed over a substrate by etching a first capacitor container opening having at least one sidewall. An electrically insulative spacer is formed over the sidewall. A second capacitor container opening is etched selectively relative to the spacer. Capacitors are then formed in the capacitor containers in a manner such that adjacent capacitors have a separation distance which is substantially no greater than the width of the spacer between the adjacent capacitors.
In one aspect, a bit line contact is formed. The bit line contact is formed as an opening that extends through a layer formed on a substrate to a node on the substrate. A first dielectric sidewall is formed in the opening and coats an interior sidewall of the opening. A second dielectric sidewall is formed in the opening and coats an interior sidewall of the first dielectric layer. A conductive plug is formed within an interior sidewall of the second dielectric layer and extends through the opening to establish electrical communication to the node.
A novel masking layout is provided which allows capacitors to be formed in a manner which reduces device pitch by almost 50%. Such is particularly adaptive for use in fabrication of DRAM circuitry.
REFERENCES:
patent: 4999689 (1991-03-01), Iguchi et al.
patent: 5496757 (1996-03-01), Rosner
patent: 5554557 (1996-09-01), Koh
patent: 5792687 (1998-08-01), Jeng et al.
patent: 5998256 (1999-12-01), Juengling
patent: 6160283 (2000-12-01), Clampitt
Hoang Quoc
Micro)n Technology, Inc.
Nelms David
Wells St. John P.S.
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