Semiconductor device manufacturing: process – Chemical etching
Reexamination Certificate
2011-03-29
2011-03-29
Garber, Charles D (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Reexamination Certificate
active
07915168
ABSTRACT:
Some embodiments include methods in which insulative material is simultaneously deposited across both a front side of a semiconductor substrate, and across a back side of the substrate. Subsequently, openings may be etched through the insulative material across the front side, and the substrate may then be dipped within a plating bath to grow conductive contact regions within the openings. The insulative material across the back side may protect the back side from being plated during the growth of the conductive contact regions over the front side. In some embodiments, plasma-enhanced atomic layer deposition may be utilized to for the deposition, and may be conducted at a temperature suitable to anneal passivation materials so that such annealing occurs simultaneously with the plasma-enhanced atomic layer deposition.
REFERENCES:
patent: 6150711 (2000-11-01), Kom et al.
patent: 6404216 (2002-06-01), Tandy
patent: 6573547 (2003-06-01), Ahn et al.
patent: 6656785 (2003-12-01), Chiang et al.
patent: 6825129 (2004-11-01), Hong
patent: 7125582 (2006-10-01), McSwiney et al.
patent: 7187085 (2007-03-01), Clevenger et al.
patent: 7489545 (2009-02-01), Forbes et al.
patent: 2004/0130035 (2004-07-01), Wu et al.
patent: 2004/0266126 (2004-12-01), Lee
patent: 2005/0009267 (2005-01-01), Belyansky et al.
patent: 2005/0255714 (2005-11-01), Iyer et al.
patent: 2005/0270822 (2005-12-01), Shrivastava et al.
patent: 2006/0017132 (2006-01-01), Birner et al.
patent: 2006/0154464 (2006-07-01), Higashi
patent: 2006/0186448 (2006-08-01), Inoue et al.
patent: 2006/0211246 (2006-09-01), Ishizaka et al.
patent: 2007/0034930 (2007-02-01), Bhattacharyya
patent: 2007/0105377 (2007-05-01), Koos et al.
patent: 2007/0111546 (2007-05-01), Iyer et al.
patent: 2007/0116887 (2007-05-01), Faguet
patent: 2007/0145454 (2007-06-01), Bhattacharyya
patent: 2007/0209590 (2007-09-01), Li
patent: 2007/0234538 (2007-10-01), Ahn
patent: 2007/0238031 (2007-10-01), Lee et al.
patent: 2007/0238316 (2007-10-01), Ohashi
patent: 2007/0251445 (2007-11-01), Ishizaka
patent: 2007/0259517 (2007-11-01), Benson et al.
patent: 2007/0278619 (2007-12-01), Clevenger et al.
patent: 2008/0081409 (2008-04-01), Song et al.
patent: 2008/0087926 (2008-04-01), Park et al.
patent: 2008/0237780 (2008-10-01), Yamazaki et al.
patent: 2009/0056994 (2009-03-01), Kuhr et al.
patent: 2432363 (2007-05-01), None
patent: 2007-150242 (2007-06-01), None
patent: WO 2004/042804 (2004-05-01), None
Chit Hwei Ng., et al. “MIM Capacitor Integration for Mixed-Signal/RF Applications” Jul. 2005 IEEE Transactions on Electron Devices, vol. 52, No. 7, pp. 1399-1409.
H.R. Huff, et al. “Integration of High-K Gate Stack Systems Into Planar CMOS Process Flows” IWGI 2001 Tokyo pp. 2-11.
H.S. Kim, et al. “An Outstanding and Highly Manfacturable 80nm DRAM Technology” May 2003, IEEE pp. IEDM 03-411-414.
Jae-Eun Park, et al. “Mass-Productive Ultra-Low Tempearture AL SiO2 Process Promising for Sub-90nm Memory and Logic Devices” Feb. 2002, IEEE, pp. 229-232 IEDM.
Kinma Kim “Technology for sub-50nm DRAM and NAND Flash Manufacturing” Aug. 2005 IEEE, 4 pages.
Kokusai “Low Temperature Nitrides” http://www.ksec.com/processes/Low—temp.htm printed Dec. 10, 2007, 2 pages.
Micron Technology, Inc. “WireBonding Techniques” Technical Note 2006, TN-29-24; Micron Wire-Bonding Techniquest Overview pp. 1-5.
Liu Junting
Ping Er-Xuan
Takedai Seiichi
Garber Charles D
Micro)n Technology, Inc.
Stevenson Andre′ C
Wells St. John P.S.
LandOfFree
Semiconductor processing methods does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor processing methods, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor processing methods will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2778930