Semiconductor processing method of forming an electrical interco

Details Semiconductor processing method of forming an electrical interco Semiconductor processing method of forming an electrical interco

1994-08-29

1996-04-09

Fourson, George

Fishing, trapping, and vermin destroying

437200, 437191, H01L 2144

Patent

active

055061729

ABSTRACT:
A semiconductor processing method includes: a) providing a substrate having a base region to which electrical connection is to be made; b) providing a first layer of a conductive first material; c) providing an etch stop layer over the first layer; d) etching a contact opening through the etch stop and first layers to the base region; e) providing a second layer of first material outwardly of the etch stop layer and within the contact opening to a thickness greater than the first layer thickness and extending outwardly beyond the contact opening upper edge; f) removing first material of the second layer and defining a second layer plug within the contact, the second layer plug having an outermost surface extending outwardly beyond the contact opening upper edge and thereby providing the second layer plug to be of greater thickness than the first layer; g) masking outwardly of the first layer and the second layer plug to define a mask pattern for definition of a circuit component from the first layer which connects with the base region through the second layer plug; and h) etching unmasked portions of the first layer and second layer plug to define a circuit component which connects with the base region through the second layer plug, the greater thickness of the second layer plug as compared to the thickness of the first layer restricting etching into the base region during etching.

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patent: 5162259 (1992-11-01), Kolar et al.
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