Semiconductor processing method of forming a pair of field effec

Details Semiconductor processing method of forming a pair of field effec Semiconductor processing method of forming a pair of field effec

1996-01-03

1997-11-25

Bowers, Jr., Charles L.

Fishing, trapping, and vermin destroying

437 52, 437 56, 437918, 437979, 148DIG14, 148DIG163, 257380, 257393, 257904, H01L 218244

Patent

active

056912170

ABSTRACT:
A method of forming a pair of field effect transistors having different thickness gate dielectric layers includes, a) providing a first region on a substrate for formation of a first field effect transistor having a first gate dielectric layer of a first thickness and providing a second region on the substrate for formation of a second field effect transistor having a second gate dielectric layer of a second thickness; b) providing the first gate dielectric layer and a first conductive gate layer over the first and second regions; c) patterning the first conductive layer to define a first gate of the first field effect transistor in the first region while leaving the first conductive layer not patterned for gate formation for the second field effect transistor in the second region; d) after defining the first gate, stripping the first conductive layer and the first gate dielectric layer from the second region; e) after stripping the first conductive layer and the first gate dielectric layer from the second region, providing the second gate dielectric layer and a second conductive gate layer over the second region; and f) patterning the second conductive layer in the second region to define a second gate of the second field effect transistor in the second region. The invention has particular utility in fabrication of SRAM circuitry.

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Research Disclosure, 334(2)(1992)117, No. 33428, "Process to make thick and thin gate dielectric devices ont he same chip", Feb. 1992.
Lage, Craig et al., "Soft Error Rate And Stored Charge Requirements in Advanced High-Density SRAMs", IEEE 1993, IEDM pp. 821-824.

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