Semiconductor process using lapped substrate and lapped low resi

Details Semiconductor process using lapped substrate and lapped low resi Semiconductor process using lapped substrate and lapped low resi

1976-10-12

1979-02-27

Larkins, William D.

Metal working

Method of mechanical manufacture

Assembling or joining

29583, 29589, 29591, 357 56, 357 71, 357 81, H01L 21304, H01L 2336

Patent

active

041411358

ABSTRACT:
A process intended for avoiding the "flip chip bonding" technique, well known for planar diodes, is provided. It is further applicable to mesa diodes and planar transistors. It comprises an essential step: the lapping of the substrate up to reduce its thickness to the same order of magnitude as the upper active layer of a semiconductor device, thus facilitating the cooling of the device through the substrate towards a heat sink. This essential step is made possible by virtue of a preliminary bonding on the upper layer of the semiconductor device of a block of silicon. According to a first alternative of the invention the block is finally eliminated and the device is a conventional one with a very thin substrate. According to a second alternative of the invention, the block is retained and lapped after addition of the heat sink, then metalized to provide a secondary way to the thermal flux.

REFERENCES:
patent: 3343255 (1967-09-01), Donovan
patent: 3445303 (1969-05-01), Engbert
patent: 3559282 (1971-02-01), Lesk
patent: 3609474 (1971-09-01), Vincent, Jr.
patent: 3689993 (1972-09-01), Tolar
patent: 3775200 (1973-11-01), DE Nobel et al.
patent: 3908187 (1975-09-01), Sheldon et al.
patent: 4035830 (1977-07-01), Kim

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