Data processing: structural design – modeling – simulation – and em – Modeling by mathematical expression
Reexamination Certificate
1998-11-25
2002-03-19
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Modeling by mathematical expression
C703S014000, C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06360190
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor process device simulation method of simulating the manufacturing process and electrical characteristics of a semiconductor device using a computer, and a storage medium storing a simulation program and, more particularly, to a simulation method of efficiently and numerically solving, on a computer, simultaneous multi-dimensional linear equations based on physical laws used for a simulation.
As semiconductor integrated circuits such as a VLSI have become smaller, manufacturing has become increasingly complicated. As a result low-temperature processing, precise annealing processing, and accurate process design are of increasing importance.
On such a background, in recent years, device simulations are generally used for development and research of, e.g., the manufacture of semiconductor devices. A factor for this is a great progress in computers which actually execute the device simulation. Additionally, more convenient interfaces for the computers are becoming available. The progress in the analysis technique allows simulations for objects in a wider range and even analysis of breakdown phenomena or current concentration in a semiconductor device.
In computer simulations of thermal impurity diffusion which is one of the manufacturing processes of a semiconductor device described in reference 1: Ryo Dan, “Process Device Simulation Technology”, pp. 26-28, first a region to be analyzed is divided into meshes, and a diffusion equation is discretely defined for each mesh point. The diffusion equations are converted into linear equations and then into simultaneous linear equations by Newton's method or the like so as to solve the diffusion equations.
The electrical characteristics of a semiconductor device prepared by manufacturing processes including thermal impurity diffusion, ion implantation, and thermal oxidation can be simulated by the method described in reference 2 (Dan Ryo, “Process Device Simulation Technology”, pp. 105-134), according to which a region to be analyzed is divided into meshes, and a Poisson equation and current continuous equation are discretely defined for each mesh point. These equations are converted into linear equations and then into simultaneous linear equations by Newton's method or the like, and the equations are solved on a computer, thereby simulating the electrical characteristics of the semiconductor device.
In these semiconductor process device simulation methods, it is important in practice to solve large scale simultaneous linear equations having as many dimensions as the number of mesh points using a computer with as small a memory and as high a speed as possible.
The function of solving these simultaneous linear equations is called a “matrix solver” for which various methods have been proposed. For example, for an equation having four dimensions factorization may be used.
And, for an equation having a large number of dimensions, an iterative method is used because of limitations on the memory capacity and calculation time needed. When the coefficient matrix of simultaneous linear equations to be solved is symmetrical, the ICCG (Incomplete Choleske and Conjugate Gradient) method is used. This is a CG (Conjugate-Gradient) method with preprocessing.
When the coefficient matrix is asymmetrical, a series of techniques called the Krylov subspace method are generally used because of advantages in convergence.
With both the ICCG and Krylov subspace methods, forming an algorithm for multiplying the original coefficient matrix with an approximate inverse matrix of the coefficient matrix of the equation to be solved permits a reduction in the number of conditions of the coefficient matrix, whereby the approximate inverse matrix of the coefficient matrix of the equation may be solved by a reduced number of iterations. This operation is called “preconditioning”, as described above. The approximate inverse matrix of the coefficient matrix is called a “preconditioning matrix”.
As the inverse matrix of the preconditioning matrix, a matrix obtained by “incomplete LU-factorization”, i.e., LU-factorization, with limited fill-in generation positions is often used. Fill-in is a process of LU-factorization represented by equations (1) and (2) below and means that at a position (i, j) where an element value A
ij
is 0 in the original coefficient matrix, a new element L
ij
or U
ij
other than 0 is generated. When the generated fill-in is not rejected, and taken into consideration in the subsequent process of
L
i
j
=
A
i
j
-
∑
k
=
1
j
-
1
L
i
k
U
k
j
(
k
<
j
<
i
)
(
1
)
U
i
j
=
L
i
i
-
1
(
A
i
j
-
∑
k
=
1
i
-
1
L
i
k
U
k
j
)
(
k
<
i
<
j
)
(
2
)
LU-factorization, conventional complete LU-factorization is performed.
In preprocessing based on incomplete LU-factorization, it is required to perform optimum processing which satisfies the following two contradictory conditions. First, fill-in generation should be minimized to suppress the amount of memory used and calculation time needed for performing the calculation. Second, a result as close as possible to complete LU-factorization should be obtained to increase convergence of the iterative method.
A conventional method of efficiently performing such processing is described in reference 3 (Shin Nakamura and Akio Nakagawa, High-speed Iterative Method for Two-dimensional Bipolar MOS Composite Device Simulator TONADDEII”, IEICE Technical Report, pp. 64-65) or reference 4 (Megumi Kawakami, Masahiro Sugaya, and Shiroo Kamohara, “A New High-speed Non-equilibrium Point Defect Model for Annealing Simulation”, SISPAD '96, p. 94, FIG. 1
a
) is used.
In the method described in reference 3 or 4, as shown in the flow chart of
FIG. 8
, first, the maximum value n of the number of equations to be solved which are defined for each point is obtained in step
801
. In step
802
, the rows and columns of the coefficient matrix are put into a group in units of square submatrices of n×n for each mesh point, thereby forming blocks of coefficient matrices. In step
803
, while virtually regarding an n×n square submatrix as one matrix, incomplete LU-factorization processing based on calculation of the square submatrices is performed.
FIG. 9
shows the structure of the coefficient matrix formed by the above operation.
With the operation in units of square submatrices, incomplete LU-factorization close to complete LU-factorization can be more effectively performed using the same memory capacity as would be in processing units of scalar elements. This is because the fill-in generation pattern is determined while giving prominence to a combination of equations at one mesh point.
Objects to which the above-described conventional semiconductor process device simulation technology is applied are disclosed in Japanese Patent Laid-Open No. 6-53155 or 8-213334.
However, the above-described conventional semiconductor process device simulation technology has the following problem. That is, when a equation is derived from a certain physical law holds for only part of an analysis region to be processed, or no equation is defined, excess memory capacity is required to process incomplete LU-factorization.
This is because in making the computer calculations, a square submatrix having a uniform size of n×n is used as the processing unit of incomplete LU-factorization. For example, in the above-described simulation, the submatrix size of n×n is maintained even at a mesh point where n equations are not defined. The computer performing the calculations must form an overall coefficient matrix while inserting “1” to the corresponding principal diagonal portions of the submatrix and set the coefficient matrix on the memory. For this reason, excess memory capacity is used.
When the computer executes i
Hayes, Soloway, Hennessey Grossman & Hage, P.C.
Jones Hugh
NEC Corporation
Teska Kevin J.
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