Semiconductor process and integrated circuit having dual...

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Including adhesive bonding step

Reexamination Certificate

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C438S217000, C438S227000, C438S231000, C438S302000, C438S305000, C257S493000, C257S497000, C257S506000, C257S511000, C257S521000

Reexamination Certificate

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06897095

ABSTRACT:
A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first gate dielectric. The first transistor has a first gate electrode and the second transistor has a second gate electrode. The first and second gate electrodes are the same in composition. The first gate dielectric and the second gate dielectric may both include high-K dielectrics such as Hafnium oxide and Aluminum oxide. The first and second gate electrodes both include a gate electrode layer overlying the respective gate dielectrics. The gate electrode layer is preferably either TaSiN and TaC. The first and second gate electrodes may both include a conductive layer overlying the gate electrode layer. In one such embodiment, the conductive layer may include polysilicon and tungsten.

REFERENCES:
patent: 5686324 (1997-11-01), Wang et al.
patent: 5827747 (1998-10-01), Wang et al.
patent: 6084279 (2000-07-01), Nguyen et al.
patent: 6528858 (2003-03-01), Yu et al.
patent: 6545324 (2003-04-01), Madhukar et al.

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