Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – For plural devices
Reexamination Certificate
2001-05-15
2003-01-14
Wilson, Allan R. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
For plural devices
C257S724000, C257S778000
Reexamination Certificate
active
06507107
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to stacked multiple die semiconductor assemblies, printed circuit board assemblies, computer systems, and their methods of assembly. More particularly, the present invention relates to an improved scheme for increasing semiconductor die density.
Conventional Chip On Board (COB) techniques used to attach semiconductor at dies to a printed circuit board include flip chip attachment, wirebonding, and tape automated bonding (“TAB”). Flip chip attachment consists of attaching a flip chip to a printed circuit board or other substrate. A flip chip is a semiconductor chip that has a pattern or array of electrical terminations or bond pads spaced around an active surface of the flip chip for face down mounting of the flip chip to a substrate. Generally, the flip chip has an active surface having one of the following electrical connectors: Ball Grid Array (“BGA”)—wherein an array of minute solder balls is disposed on the surface of a flip chip that attaches to the substrate (“the attachment surface”); Slightly Larger than Integrated Circuit Carrier (“SLICC”)—which is similar to a BGA, but having a smaller solder ball pitch and diameter than a BGA; or a Pin Grid Array (“PGA”)—wherein an array of small pins extends substantially perpendicularly from the attachment surface of a flip chip. The pins conform to a specific arrangement on a printed circuit board or other substrate for attachment thereto.
With the BGA or SLICC, the solder or other conductive ball arrangement on the flip chip must be a mirror-image of the connecting bond pads on the printed circuit board such that precise connection is made. The flip chip is bonded to the printed circuit board by refluxing the solder balls. The solder balls may also be replaced with a conductive polymer. With the PGA, the pin arrangement of the flip chip must be a mirror-image of the pin recesses on the printed circuit board. After insertion, the flip chip is generally bonded by soldering the pins into place. An under-fill encapsulant is generally disposed between the flip chip and the printed circuit board for environmental protection and to enhance the attachment of the flip chip to the printed circuit board. A variation of the pin-in-recess PGA is a J-lead PGA, wherein the loops of the J's are soldered to pads on the surface of the circuit board.
Wirebonding and TAB attachment generally begin with attaching a semiconductor chip to the surface of a printed circuit board with an appropriate adhesive, such as an epoxy. In wirebonding, bond wires are attached, one at a time, to each bond pad on the semiconductor chip and extend to a corresponding lead or trace end on the printed circuit board. The bond wires are generally attached through one of three industry-standard wirebonding techniques: ultrasonic bonding-using a combination of pressure and ultrasonic vibration bursts to form a metallurgical cold weld; thermocompression bonding-using a combination of pressure and elevated temperature to form a weld; and thermosonic bonding-using a combination of pressure, elevated temperature, and ultrasonic vibration bursts. The semiconductor chip may be oriented either face up or face down (with its active surface and bond pads either up or down with respect to the circuit board) for wire bonding, although face up orientation is more common. With TAB, ends of metal leads carried on an insulating tape such as a polyamide are respectively attached to the bond pads on the semiconductor chip and to the lead or trace ends on the printed circuit board. An encapsulant is generally used to cover the bond wires and metal tape leads to prevent contamination.
Higher performance, lower cost, increased miniaturization of components, and greater packaging density of integrated circuits are ongoing goals of the computer industry. As new generations of integrated circuit products are released, the number of devices used to fabricate them tends to decrease due to advances in technology even though the functionality of these products increases. For example, on the average, there is approximately a 10 percent decrease in components for every product generation over the previous generation with equivalent functionality.
In integrated circuit packaging, in addition to component reduction, surface mount technology has demonstrated an increase in semiconductor chip density on a single substrate or board despite the reduction of the number of components. This results in more compact designs and form factors and a significant increase in integrated circuit density. However, greater integrated circuit density is primarily limited by the space or “real estate” available for mounting dies on a substrate, such as a printed circuit board.
U.S. Pat. Nos. 5,994,166 and 6,051,878, the disclosures of which are incorporated herein by reference, represent a number of schemes for increasing semiconductor chip density on a single substrate or board. Despite the advantages of & the most recent developments in semiconductor fabrication there is a continuing need for improved schemes for increasing semiconductor die density in printed circuit board assemblies.
BRIEF SUMMARY OF THE INVENTION
This need is met by the present invention wherein an improved semiconductor die assembly scheme is provided. In accordance with one embodiment of the present invention, a multiple die semiconductor assembly is provided comprising first and second semiconductor dies, and an intermediate substrate. The first semiconductor die defines a first active surface including at least one conductive bond pad. The second semiconductor die defines a second active surface including at least one conductive bond pad. The intermediate substrate is positioned between the first active surface of the first semiconductor die and the second active surface of the second semiconductor die such that a first surface of the intermediate substrate faces the first active surface and such that a second surface of the intermediate substrate faces the second active surface. The first semiconductor die is electrically coupled to the intermediate substrate by at least one topographic contact extending from the first active surface to the first surface of the intermediate substrate. The second surface of the intermediate substrate includes a cavity defined therein. The intermediate substrate defines a passage there through. The second semiconductor die is secured to the second surface of the intermediate substrate within the cavity such that the conductive bond pad of the second semiconductor die is aligned with the passage. The second semiconductor die is electrically coupled to the intermediate substrate by at least one conductive line extending from the conductive bond pad of the second semiconductor die through the passage defined in the intermediate substrate and to a conductive contact on the first surface of the intermediate substrate.
Accordingly, it is an object of the present invention to provide an improved semiconductor die assembly scheme. Other objects of the present invention will be apparent in light of the description of the invention embodied herein.
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paten
Killworth, Gottman Hagan & Schaeff, L.L.P.
Micro)n Technology, Inc.
Wilson Allan R.
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